Abstract
Power-efficient scheduling is investigated for BiNoC architecture in this chapter. To minimize the power consumption of real time applications on BiNoC, time slacks in a preliminary schedule are exploited to conserve power. In addition to the processing units, wide variance in the link utilization of an NoC also leads to huge power saving if the link frequency can be tuned accurately to track the variations in bandwidth requirements. This can be accomplished by utilizing the DVS technique to scale the link voltage or frequency, as long as the deadline is met. An efficient power aware task and communication scheduling algorithm is proposed with a unique feature of utilizing the configurability of a bidirectional channel to trade the data transmission time for power expenditure. Extensive simulations are performed to compare the proposed algorithm against conventional Earliest-Deadline First (EDF) based algorithm on NoC.
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References
G. Varatkar and R. Marculescu, “Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization,” in Proceedings of the International Conference on Computer-Aided Design, pp. 510-517, November 2003
J. Hu and R. Marculescu, “Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 234-239, February 2004
R. Mullins, A. West, and S. Moore, “Low-Latency Virtual-Channel Routers for On-Chip Networks,” in Proceedings of the International Symposium on Computer Architecture, pp. 188-197, June 2004
KK. Kim, S. J. Lee, K. Lee, and H. J. Yoo, “An Arbitration Look-ahead Scheme for Reducing End-to-End Latency in Networks-on-Chip.” in Proceedings of the International Symposium on Circuits and Systems, pp. 2357-2360, May 2005
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Chen, SJ., Lan, YC., Tsai, WC., Hu, YH. (2012). Energy-Aware Application Mapping for BiNoC. In: Reconfigurable Networks-on-Chip. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9341-0_9
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DOI: https://doi.org/10.1007/978-1-4419-9341-0_9
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