Abstract
A photonic network design encompasses a wide range of details that must be considered carefully. Design details include material system, layout of components, and network arbitration mechanisms. Each detail involves several metrics including performance requirements, power constraints, scalability, and cost. Designing a photonic network which is both feasible and cost-effective is a multi-dimensional design-space problem in which all the parts are tightly coupled.
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References
J. Chan and K. Bergman, “Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications,” Optical Communications and Networking, IEEE/OSA Journal of, vol. 4, no. 3, pp. 189–201, Mar. 2012.
G. Hendry, E. Robinson, V. Gleyzer, J. Chan, L. P. Carloni, N. Bliss, and K. Bergman, “Circuit-switched memory access in photonic interconnection networks for high-performance embedded computing,” in International Conference for High Performance Computing, Networking, Storage, and Analysis (Supercomputing), Nov. 2010.
A. Shacham, K. Bergman, and L. Carloni, “On the design of a photonic network-on-chip,” in First International Symposium on Networks-on-Chip, 2007.
H. Wang, B. G. Lee, A. Shacham, and K. Bergman., “On the design of a \(4\times 4\) nonblocking nanophotonic switch for photonic networks on chip,” in Proceedings of Frontiers in Nanophotonics and Plasmonics, 2007.
J. Chan, A. Biberman, B. G. Lee, and K. Bergman, “Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications,” in IEEE Lasers and Electro-Optics Society (LEOS), Nov. 2008.
A. Shacham, K. Bergman, and L. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” Computers, IEEE Transactions on, vol. 57, no. 9, pp. 1246–1260, Sep 2008.
S. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, J. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Hoskote, N. Borkar, and S. Borkar, “An 80-tile sub-100-W teraflops processor in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 43, no. 1, pp. 29–41, Jan.
F. Xia, L. Sekaric, and Y. Vlasov, “Ultracompact optical buffers on a silicon chip,” Nature Photonics, vol. 1, pp. 65–71, Jan. 2007.
W. Bogaerts, P. Dumon, D. V. Thourhout, and R. Baets, “Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides,” Opt. Lett., vol. 32, no. 19, pp. 2801–2803, 2007.
B. G. Lee, A. Biberman, P. Dong, M. Lipson, and K. Bergman, “All-optical comb switch for multiwavelength message routing in silicon photonic networks,” IEEE Photonics Technology Letters, vol. 20, no. 10, pp. 767–769, May 2008.
J. Chan, G. Hendry, A. Biberman, and K. Bergman, “Architectural exploration of chip-scale photonic interconnection network designs using physical-layer analysis,” Lightwave Technology, Journal of, vol. 28, no. 9, pp. 1305–1315, May 2010.
N. Sherwood-Droz, H. Wang, L. Chen, B. G. Lee, A. Biberman, K. Bergman, and M. Lipson, “Optical \(4\times 4\) hitless silicon router for optical networks-on-chip (NoC),” Opt. Express, vol. 16, no. 20, pp. 15 915–15 922, Sep. 2008.
M. Uenuma and T. Motooka, “Temperature-independent silicon waveguide optical filter,” Opt. Lett., vol. 34, no. 5, pp. 599–601, Mar. 2009.
T. Gensty, W. Elsäßer, and C. Mann, “Intensity noise properties of quantum cascade lasers,” Opt. Express, vol. 13, no. 6, pp. 2032–2039, 2005.
Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, “12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators,” OSA Optics Express, vol. 15, no. 2, pp. 430–436, 2007.
K. Preston, S. Manipatruni, A. Gondarenko, C. B. Poitras, and M. Lipson, “Deposited silicon high-speed integrated electro-optic modulator,” Opt. Express, vol. 17, no. 7, pp. 5118–5124, Mar. 2009.
P. Lathi, Modern Digital and Analog Communication Systems, 3rd ed. Oxford University Press, 1998.
G. Hendry et al., “Analysis of photonic networks for a chip-multiprocessor using scientific applications,” in The 3rd ACM/IEEE International Symposium on Networks-on-Chip, May 2009.
H. Wang et al., “ORION: A power-performance simulator for interconnection networks,” in 35th International Symposium on Microarchitecture, 2002.
A. Biberman, J. Chan, and K. Bergman, “On-chip optical interconnection network performance evaluation using power penalty metrics from silicon photonic modulators,” in Interconnect Technology Conference (IITC), 2010 International, Jun. 2010, pp. 1–3.
P. Kumar, Y. Pan, J. Kim, G. Memik, and A. Choudhary, “Exploring concentration and channel slicing in on-chip network router,” in NOCS ’09: Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009, pp. 276–285.
Cactus Computational Toolkit, [Online]:http://www.cactuscode.org/.
Z. Lin, S. Ethier, T. S. Hahm, and W. M. Tang, “Size scaling of turbulent transport in magnetically confined plasmas,” Physical Review Letters, vol. 88, no. 19, p. 195004, Apr. 2002.
A. Canning, L. Wang, A. Williamson, and A. Zunger, “Parallel empirical pseudopotential electronic structure calculations for million atom systems,” Journal of Computational Physics, vol. 160, no. 1, pp. 29–41, 2000.
J. Borrill, J. Carter, L. Oliker, and D. Skinner, “Integrated performance monitoring of a cosmology application on leading HEC platforms,” in Proceedings of the 2005 International Conference on Parallel Processing, 2005, pp. 119–128.
N. Travinin, H. Hoffmann, R. Bond, H. Chan, J. Kepner, and E. Wong, “pMapper: Automatic mapping of parallel Matlab programs,” in \({\mathit{DOD}}\_{\mathit{UGC}}\) ’05: Proceedings of the 2005 Users Group Conference on 2005 Users Group Conference, 2005, p. 254.
H. Kim, E. Rutledge, S. Sacco, S. Mohindra, M. Marzilli, J. Kepner, R. Haney, J. Daly, and N. Bliss, “Pvtol: Providing productivity, performance and portability to DoD signal processing applications on multicore processors,” in HPCMP-UGC ’08: Proceedings of the 2008 DoD HPCMP Users Group Conference, 2008, pp. 327–333.
V. Strassen, “Gaussian elimination is not optimal.” Numerische Mathematik, vol. 14, no. 3, pp. 354–356, 1969.
J. W. Cooley and J. W. Tukey, “An algorithm for the machine calculation of complex fourier series,” Mathematics of Computation, vol. 19, pp. 297–301, 1965.
A. Biberman, K. Preston, G. Hendry, J. Chan, N. Sherwood-Droz, J. Levy, M. Lipson, K. Bergman, “Photonic network-on-chip architecture using multi-layer deposited silicon materials for high-performance chip multiprocessors.” Journal of Emerging Technologies in, Computing Systems, 2011.
D.-X. Xu, A. Delâge, R. McKinnon, M. Vachon, R. Ma, J. Lapointe, A. Densmore, P. Cheben, S. Janz, and J. H. Schmid, “Archimedean spiral cavity ring resonators in silicon as ultra-compact optical comb filters,” Opt. Express, vol. 18, no. 3, pp. 1937–1945, 2010.
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Bergman, K., Carloni, L.P., Biberman, A., Chan, J., Hendry, G. (2014). Photonic Network Architectures I: Circuit Switching. In: Photonic Network-on-Chip Design. Integrated Circuits and Systems, vol 68. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9335-9_5
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DOI: https://doi.org/10.1007/978-1-4419-9335-9_5
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