Abstract
Interframe prediction in H.264/AVC is carried out in three phases: integer motion estimation (IME), fractional motion estimation, and motion compensation. We will discuss these functions in this chapter and Chaps.4 and 5, respectively. Because motion estimation in H.264/AVC supports variable block sizes and multiple reference frames, high computational complexity and huge data traffic become main difficulties in VLSI implementation. Moreover, high-resolution video applications, such as HDTV, make these problems more critical. Therefore, current VLSI designs usually adopt parallel architecture to increase the total throughput and solve high computational complexity. On the other hand, many data-reuse schemes try to increase data-reuse ratio and, hence, reduce required data traffic. In this chapter, we will introduce several key points of VLSI implementation for IME.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Chen T-C, Chien S-Y, Huang Y-W, Tsai C-H, Chen C-Y, Chen T-W, Chen L-G (2006) Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder. IEEE Trans Circuits Syst Video Technol 16(6):673–688
He Z, Liou M-I (1997) Reducing hardware complexity of motion estimation algorithms using truncated pixels. In: Proceedings of IEEE international symposium on circuits and systems, Hong Kong, China, June 1997, pp 2809–2812
Huang Y-W, Wang T-C, Hsieh B-Y, Chen L-G (2003) Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264. In: Proceedings of IEEE international symposium on circuits and systems, Bangkok, Thailand, May 2003, pp II796–II799
Kao C-Y, Lin Y-L (2008) A high-performance and memory-efficient architecture for H.264/AVC motion estimation. In: Proceedings of IEEE international conference on multimedia and expo, Hanover, Germany, June 2008, pp 141–144
Kao C-Y, Lin Y-L (in press) A memory-efficient and highly parallel architecture for variable block size integer motion estimation in H264/AVC. IEEE Trans Very Large Scale Integr Syst
Kim M, Hwang I, Chae S-I (2005) A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. In: Proceedings of Asia and South Pacific design automation conference, Shanghai, China, January 2005, pp 631–634
Koga T, Iinuma K, Hirano A, Iijima Y, Ishiguro T (1981) Motion compensated interframe coding for video conferencing. In: Proceedings of national telecommunication conference, New Orleans, USA, November 1981, pp C9.6.1–C9.6.5
Komerek T, Pirsch P (1989) Array architectures for block matching algorithms. IEEE Trans Circuits Syst Video Technol 36(10):1301–1308
Lin C-C, Lin Y-K, Chang T-S (2007) PMRME: a parallel multi-resolution motion estimation algorithm and architecture for HDTV sized H.264 video coding. In: Proceedings of IEEE international conference on acoustics, speech, and signal processing, Hawaii, USA, April 2007, pp 285–288
Su C-L, Yang W-S, Chen Y-L, Yang Y-C, Chen C-W, Guo J-I, Tseng S-Y (2006) A low complexity high quality interger motion estimation architecture design for H.264/AVC. Proceedings of IEEE Asia Pacific conference on circuits and systems, Singapore, December 2006, pp 398-401
Tham J, Ranganath S, Ranganath M, Kassim A (1998) A novel unrestricted center-biased diamond search algorithm for block motion estimation. IEEE Trans Circuits Syst Video Technol 8(4):369–377
Tuan J-C, Chang T-S, Jen C-W (2002) On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. IEEE Trans Circuits Syst Video Technol 12(1):61–72
Vos L, Stegherr M (1989) Parameterizable VLSI architectures for the full-search block-matching algorithm. IEEE Trans Circuits Syst 36(10):1309–1316
Yap S, McCanny J (2004) A VLSI architecture for variable block size video motion estimation. IEEE Trans Circuits Syst II, Express Briefs 51(7):384–389
Yang K-M, Sun M-T, Wu L (1989) A family of VLSI designs for the motion compensation block-matching algorithm. IEEE Trans Circuits Syst Video Technol 36(10):1317–1325
Yeo H, Hu Y-H (1995) A novel modular systolic array architecture for full-search block matching motion estimation. IEEE Trans Circuits Syst Video Technol 5(5):407-416
Zhu S, Ma K (1997) A new diamond search algorithm for fast block matching motion estimation. In: Proceedings of international conference on information, communications and signal processing, Singapore, September 1997, pp 292–296
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Lin, YL.S., Kao, CY., Kuo, HC., Chen, JW. (2010). Integer Motion Estimation. In: VLSI Design for Video Coding. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0959-6_3
Download citation
DOI: https://doi.org/10.1007/978-1-4419-0959-6_3
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-0958-9
Online ISBN: 978-1-4419-0959-6
eBook Packages: EngineeringEngineering (R0)