Abstract
This monograph has presented a comprehensive look at the noise problems within IC packaging. Todays integrated circuits are experiencing a dramatic increase in performance due to significant advances in the IC design and fabrication processes. IC technology has followed Moores Laws for the past 30 years and is expected to continue at this rate sometime into the next decade. At the same time, IC packaging technology has evolved at a much slower pace. This mismatch in performance between the IC and the package is now the leading limitation to system performance. Inter-chip busses that transfer data between ICs within the system need to be slowed so as to avoid unwanted noise from the package. Off-chip communication is now the largest bottleneck in modern digital systems design.
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© 2010 Springer Science+Business Media, LLC
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Duan, C., LaMeres, B., Khatri, S. (2010). Summary of Off-Chip Crosstalk Avoidance. In: On and Off-Chip Crosstalk Avoidance in VLSI Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0947-3_17
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DOI: https://doi.org/10.1007/978-1-4419-0947-3_17
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Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-0946-6
Online ISBN: 978-1-4419-0947-3
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