Abstract
A process variation tolerant design approach for combinational circuits is presented in this chapter, which exploits the fact that random variations can cause a significant mismatch in two identical devices placed next to each other on the die. In this approach, a large gate is implemented using an appropriate number ( > 1) of smaller gates, whose inputs and outputs are connected to each other in parallel. This parallel connection of smaller gates to form a larger gate is referred to as a parallel gate. Since the L and V T variations are largely random and have independent variations in smaller gates, the variation tolerance of the parallel gate is improved. The parallel gates are implemented as single layout cells. By careful diffusion sharing in the layout of the parallel gates, it is possible to reduce the input and output capacitance of the gates, thereby improving the nominal circuit delay as well. An algorithm is also developed to selectively replace critical gates in a circuit by their parallel counterparts, to improve the variation tolerance of the circuit. Monte-Carlo simulations demonstrate that this process variation tolerant design approach achieves significant improvements in circuit level variation tolerance.
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Garg, R., Khatri, S.P. (2010). A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates. In: Analysis and Design of Resilient VLSI Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0931-2_9
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DOI: https://doi.org/10.1007/978-1-4419-0931-2_9
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