Abstract
With decreasing device feature sizes, reduced supply voltages, and increasing operating frequencies, very large scale integration (VLSI) systems are becoming susceptible to effects such as power and ground noise, capacitive coupling noise, radiation particle strikes or single event effects (SEE), etc. Radiation particle strikes affect the transient electrical behavior of a circuit and can result in functional errors. At the same time, with device scaling, the variations of key device parameters are increasing at an alarming rate. Because of this, it is becoming difficult to predict the performance of a VLSI design. Thus, both these issues (radiation particle strikes and process variations) result in unpredictable behavior of circuits and hence severely degrade the reliability of VLSI systems. Because of the widespread use of modern VLSI systems, it is necessary to address these issues during the design phase, to improve system reliability and resilience to radiation strikes and process variations. This is the focus of this monograph. This chapter provides background information about radiation particle strikes and process variations, and it describes how these issues affect VLSI circuit operation. This information will aid in understanding the analysis and design approaches presented in the remainder of this monograph. The goals of this monograph are also presented in this chapter along with an outline of the remaining chapters.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
T. May and M. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Transaction on Electron Devices, vol. ED-26, pp. 2–9, Jan 1979.
J. Pickle and J. Blandford, “CMOS RAM cosmic-ray-induced error rate analysis,” IEEE Transactions on Nuclear Science, vol. NS-29, pp. 3962–3967, 1981.
W. Massengill, M. Alles, and S. Kerns, “SEU error rates in advanced digital CMOS,” in Proc. of the European Conf. on Radiation and Its Effects on Components and Systems, Sep. 1993, pp. 546–553.
P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, “Modeling the effect of technology trends on the soft error rate of combinational logic,” in Proc. of the Intl. Conf. on Dependable Systems and Networks, 2002, pp. 389–398.
Q. Zhou and K. Mohanram, “Transistor sizing for radiation hardening,” in Proc. of the Intl. Reliability Physics Symposium, April 2004, pp. 310–315.
P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, and S. Borkar, “Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-um to 90-nm generation,” in International Electron Devices Meeting, Dec. 2003, pp. 21.5.1–21.5.4.
S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation,” IEEE Micro, vol. 25, no. 6, pp. 10–16, Nov.-Dec. 2005.
M. Orshansky, S. R. Nassif, and D. Boning, Design for manufacturability and statistical design: A constructive approach, US Springer, 2008.
K. Agarwal and S. Nassif, “Characterizing process variation in nanometer CMOS,” in Proc. of the Design Automation Conf., June 2007, pp. 396–399.
K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, “High-performance CMOS variability in the 65-nm regime and beyond,” IBM Journal of Research and Development, vol. 50, pp. 433–449, July/Sept. 2006.
P. E. Dodd and L. W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583– 602, 2003.
Q. Zhou and K. Mohanram, “Gate sizing to radiation harden combinational logic,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 1, pp. 155–166, Jan. 2006.
D. Binder, C. Smith, and A. Holman, “Satellite anomalities from galactic cosmic rays,” IEEE Transactions on Nuclear Science, vol. NS-22, pp. 2675–2680, Dec. 1975.
R. G. Harrison and D. B. Stephenson, “Detection of a galactic cosmis ray influence on clouds,” Geophysical Research Abstracts, vol. 8, no. 07661, pp. 1, 2006.
G. Cellere, A. Paccagnella, A. Visconti, and M. Bonanomi, “Soft errors induced by single heavy ions in floating gate memory arrays,” in Proc. of the Intl. Symposium on Defect and Fault Tolerance in VLSI Systems, 2005, pp. 275–284.
A. Johnston, “Scaling and technology issues for soft error rate,” in Proc. of the Annual Research Conf. on Reliability, Oct. 2000, pp. 1–8.
L. D. Edmonds, “A simple estimate of funneling-assisted charge collection,” IEEE Transactions on Nuclear Science, vol. 38, no. 2, pp. 828–833, Apr 1991.
P. E. Dodd, F. W. Sexton, and P. S. Winokur, “Three-dimensional simulation of charge collection and multiple-bit upset in Si devices,” IEEE Transactions on Nuclear Science, vol. 41, pp. 2005–2017, 1994.
P. E. Dodd, “Device simulation of charge collection and single-event upset,” IEEE Transactions on Nuclear Science, vol. 43, no. 2, pp. 561–575, Apr. 1996.
G. Messenger, “Collection of charge on junction nodes from ion tracks,” IEEE Transactions on Nuclear Science, vol. 29, no. 6, pp. 2024–2031, 1982.
O. A. Amusan, “Analysis of single event vulnerabilities in a 130 nm CMOS technology,” M.S. thesis, Vanderbilt University, 2006.
S. DasGupta, “Trends in single event pulse widths and pulse shapes in deep submicron CMOS,” M.S. thesis, Vanderbilt University, 2008.
G. E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, pp. 1–4, April 1965.
R. E. Kessler, “The Alpha 21264 microprocessor,” IEEE Micro, vol. 19, no. 2, pp. 24–36, 1999.
H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spatial correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467–1482, Sept. 2005.
L. He, A. B. Kahng, K. H. Tam, and J. Xiong, “Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random Leff variation,” Proc. of the Intl. Conf. on Computer-Aided Design, vol. 26, no. 5, pp. 845–857, May 2007.
K. Cao, S. Dobre, and J. Hu, “Standard cell characterization considering lithography induced variations,” in Proc. of the Design Automation Conf., 2006, pp. 801–804.
K. J. Kuhn, “Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS,” in International Electron Devices Meeting, Dec. 2007, pp. 471–474.
S. Nassif, “Delay variability: Sources, impacts and trends,” in Proc. of the Intl. Solid State Circuits Conf., 2000, pp. 368–369.
W. Zhao, Y. Cao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, and K. Nowka, “Rigorous extraction of process variations for 65nm CMOS design,” in Proc. of the European Solid State Device Research Conf., Sept. 2007.
K. Agarwal, F. Liu, C. McDowell, S. Nassif, K. Nowka, M. Palmer, D. Acharyya, and J. Plusquellic, “A test structure for characterizing local device mismatches,” in Proc. of the Symposium on VLSI Circuits, 2006, pp. 67–68.
R. Garg, C. Nagpal, and S. P. Khatri, “A fast, analytical estimator for the SEU-induced pulse width in combinational designs,” in Proc. of the Design Automation Conf., June 2008, pp. 918–923.
R. Garg and S. P. Khatri, “Efficient analytical determination of the SEU-induced pulse shape,” in Proc. of the Asia and South Pacific Design Automation Conf., Jan. 2009.
R. Garg, P. Li, and S. P. Khatri, “Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs),” in Proc. of the Intl. Symposium on Circuits and Systems, May 2008, pp. 1788–1791.
R. Garg, N. Jayakumar, S. P. Khatri, and G. Choi, “A design approach for radiation-hard digital electronics,” in Proc. of the Design Automation Conf., July 2006, pp. 773–778.
R. Garg and S. P Khatri, “A novel, highly SEU tolerant digital circuit design approach,” in Proc. of the Intl. Conf. on Computer Design, Oct. 2008, pp. 14–20.
K. Mohanram, “Closed-form simulation and robustness models for SEU-tolerant design,” in Proc. of the VLSI Test Symposium, 2005, pp. 327–333.
L. Nagel, “Spice: A computer program to simulate computer circuits,” in University of California, Berkeley UCB/ERL Memo M520, May 1995.
B. Zhang, A. Arapostathis, S. Nassif, and M. Orshansky, “Analytical modeling of SRAM dynamic stability,” in Proc. of the Intl. Conf. on Computer-Aided Design, Nov. 2006, pp. 315–322.
Synopsys Inc., Mountain View, CA, Sentaurus user’s manuals, 2007.12 edition.
Q. A. Khan, S. K. Wadhwa, and K. Misri, “A single supply level shifter for multi voltage systems,” in Proc. of the Intl. Conf. on VLSI Design, Jan. 2006, pp. 1–4.
Author information
Authors and Affiliations
Corresponding authors
Rights and permissions
Copyright information
© 2010 Springer-Verlag US
About this chapter
Cite this chapter
Garg, R., Khatri, S.P. (2010). Introduction. In: Analysis and Design of Resilient VLSI Circuits. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-0931-2_1
Download citation
DOI: https://doi.org/10.1007/978-1-4419-0931-2_1
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-0930-5
Online ISBN: 978-1-4419-0931-2
eBook Packages: EngineeringEngineering (R0)