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Towards Nanoelectronics Processor Architectures

  • W. Rao
  • A. Orailoglu
  • R. Karri
Part of the Frontiers in Electronic Testing book series (FRET, volume 37)

CMOS technology has moved beyond 80 nanometers in scale, and according to the International Technology Roadmap for Semiconductors (ITRS), is projected to reach beyond 22 nanometers in the next several years [1, 2]. At nanometer scale, CMOS devices start to meet the physical limits and further shrinking in the CMOS feature sizes is checkmated by the insurmountable barriers of quantum effects, leakage current and power consumption.

Keywords

Parent Instruction Hardware Resource Fault Rate Transient Fault Speculative Branch 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    ITRS, International Technology Roadmap for Semiconductors Emerging Research Devices, 2006.Google Scholar
  2. 2.
    European Commission, Technology Roadmap for Nanoelectronics, 2001.Google Scholar
  3. 3.
    P. Avouris, J. Appenzeller, R. Martel and S. Wind, “Carbon Nanotube Elec- tronics”, Proceedings of the IEEE, vol. 91, n. 11, pp. 1772-1784, 2003.CrossRefGoogle Scholar
  4. 4.
    P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad, “Digital Circuit Applications of Resonant Tunneling Devices”, Proceedings of the IEEE, vol. 86, n. 4, pp. 664-686, April 1998.CrossRefGoogle Scholar
  5. 5.
    C. S. Lent, P. D. Tougaw, W. Porod and G. H. Bernstein, “Quantum Cellular Automata”, Nanotechnology, vol. 4, pp. 49-57, 1993.CrossRefGoogle Scholar
  6. 6.
    M. A. Kastner, “The Single-Electron Transistor”, Review of Modern Physics, vol. 64, pp. 849-858, 1992.CrossRefGoogle Scholar
  7. 7.
    R. H. Chen, A. N. Korotkov and K. K. Likharev, “Single-electron Transistor Logic”, Applied Physics Letters, vol. 68, n. 14, April 1996.Google Scholar
  8. 8.
    J. C. Ellenbogen and J. C. Love, “Architectures for Molecular Electronic Computers: 1. Logic Structures and an Adder Designed from Molecular Electronic Diodes”, Proceedings of the IEEE, vol. 88, n. 3, pp. 386-425, 2000.CrossRefGoogle Scholar
  9. 9.
    Y. G. Krieger, “Molecular Electronics: Current State and Future Trends”, Journal of Structural Chemistry, vol. 34, pp. 896-904, 1993.CrossRefGoogle Scholar
  10. 10.
    M. R. Stan, P. D. Franzon, S. C. Goldstein, J. C. Lach and M. M. Ziegler, “Molecular Electronics: From Devices and Interconnect to Circuits and Architecture”, Proceedings of the IEEE, vol. 91, n. 11, pp. 1940-1957, November 2003.CrossRefGoogle Scholar
  11. 11.
    C. P. Collier, E. W. Wong, M. Belohradsky, F. M. Raymo, J. F. Stoddart, P. J. Kuekes, R. S. Williams and J. R. Heath, “Electronically Configurable Molecular-Based Logic Gates”, Science, vol. 285, pp. 391-394, July 1999.CrossRefGoogle Scholar
  12. 12.
    S. A. Wolf, D. D. Awschalom, R. A. Buhrman, J. M. Daughton, S. von Molnar, M. L. Roukes, A. Y. Chtchelkanova and D. M. Treger, “Spintronics: A Spin Based Electronics Vision for the Future”, Science, vol. 294, pp. 1488-1495, November 2001.CrossRefGoogle Scholar
  13. 13.
    Y. Huang, X. Duan, Y. Cui, L. J. Jauhon, K. Kim and C. M. Lieber, “Logic Gates and Computation from Assembled Nanowire Building Blocks”, Science, vol. 294, pp. 1313-1317, November 2001.CrossRefGoogle Scholar
  14. 14.
    P. J. Kuekes, D. R. Stewart and R. S. Williams, “The Crossbar Latch: Logic Value Storage, Restoration, and Inversion in Crossbar Circuits”, Journal of Applied Physics, vol. 97, n. 3, pp. 034301, July 2005.CrossRefGoogle Scholar
  15. 15.
    G. Snider, P. J. Kuekes and R. S. Williams, “CMOS-like Logic in Defective, Nanoscale Crossbars”, Nanotechnology, vol. 15, pp. 881-891, August 2004.CrossRefGoogle Scholar
  16. 16.
    G. Snider and W. Robinett, “Crossbar Demultiplexers for Nanoelectronics Based on n-Hot Codes”, IEEE Transactions on Nanotechnology, vol. 4, pp. 249-254, 2005.CrossRefGoogle Scholar
  17. 17.
    A. DeHon and M. J. Wilson, “Nanowire-based Sublithographic Programmable Logic Arrays”, in FPGA, pp. 123-132, 2004.Google Scholar
  18. 18.
    A. DeHon, “Array-Based Architecture for FET-Based, Nanoscale Electronics”, IEEE Transactions on Nanotechnology, vol. 2, n. 1, pp. 23-32, 2003.CrossRefMathSciNetGoogle Scholar
  19. 19.
    D. B. Strukov and K. K. Likharev, “CMOL FPGA: A Reconfigurable Architecture for Hybrid Digital Circuits with Two-terminal Nanodevices”, Nanotechnology, vol. 16, pp. 888-900, April 2005.CrossRefGoogle Scholar
  20. 20.
    D. B. Strukov and K. K. Likharev, “A Reconfigurable Architecture for Hybrid CMOS/Nanodevice Circuits”, in ACM FPGA, pp. 131-140, 2006.Google Scholar
  21. 21.
    P. Beckett and A. Jennings, “Towards Nanocomputer Architecture”, in AsiaPacific Computer System Architecture Conference, pp. 141-150, 2002.Google Scholar
  22. 22.
    K. Nikolic, A. Sadek and M. Forshaw, “Architectures for Reliable Computing with Unreliable Nanodevices”, in Proceedings of the 1st IEEE Conference on Nanotechnology, pp. 254-259, 2001.Google Scholar
  23. 23.
    J. R. Heath, P. J. Kuekes, G. S. Snider and S. Williams, “A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology”, Science, vol. 280, pp. 1716-1721, June 1998.CrossRefGoogle Scholar
  24. 24.
    S. C. Goldstein and M. Budiu, “NanoFabrics: Spatial Computing Using Molecular Electronics”, in ISCA, pp. 178-191, 2001.Google Scholar
  25. 25.
    S. C. Goldstein, M. Budiu, M. Mishra and G. Venkataramani, “Reconfigurable Computing and Electronic Nanotechnology”, in ASAP, pp. 132-143, 2003.Google Scholar
  26. 26.
    M. S. Montemerlo, J. C. Love, G. J. Opitech, D. G. Gordon and J. C. Ellenbogen, Technologies and Designs for Electronic Nanocomputers, MITRE, July 1996.Google Scholar
  27. 27.
    T. Juhnke and H. Klar, “Calculation of the Soft Error Rate of Submicron CMOS Logic Circuits”, IEEE Journal of Solid-State Circuits, vol. 30, n. 7, pp. 830-834, July 1995.CrossRefGoogle Scholar
  28. 28.
    T. Karnik, P. Hazucha and J. Patel, “Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes”, IEEE Transactions on Dependable and Secure Computing, vol. 1, pp. 128-143, April-June 2004.CrossRefGoogle Scholar
  29. 29.
    P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger and L. Alvisi, “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic”, in DSN, pp. 1112-1119, 2002.Google Scholar
  30. 30.
    M. Forshaw, R. Stadler, D. Crawley and K. Nikolic, “A Short Review of Nanoelectronic Architectures”, Nanotechnology, vol. 15, pp. 220-223, 2004.CrossRefGoogle Scholar
  31. 31.
    K. Nikolic, A. Sadek and M. Forshaw, “Fault-tolerant Techniques for Nanocomputers”, Nanotechnology, vol. 13, pp. 357-362, 2002.CrossRefGoogle Scholar
  32. 32.
    J. von Neumann, “Probabilistic Logics and the Synthesis of Reliable Organ- isms from Unreliable Components”, in C. Shannon and J. McCarthy, editors, Automata Studies, Princeton University Press, Princeton, 1956.Google Scholar
  33. 33.
    J. Han and P. Jonker, “A System Architecture Solution for Unreliable Nanoelectronic Devices”, IEEE Transactions on Nanotechnology, vol. 1, n. 4, pp. 201-208, December 2002.CrossRefGoogle Scholar
  34. 34.
    J. Han, J. Gao, Y. Qi, P. Jonker and J. A. B. Fortes, “Toward Hardware- Redundant, Fault-Tolerant Logic for Nanoelectronics”, IEEE Design and Test of Computers, vol. 22, n. 4, pp. 328-339, July-August 2005.CrossRefGoogle Scholar
  35. 35.
    T. M. Austin, “DIVA: A Reliable Substrate for Deep Submicron Microarchi- tecture Design”, in ACM/IEEE Annual Symposium on Microarchitecture, pp. 196-207, 1999.Google Scholar
  36. 36.
    P. Agrawal, “Fault Tolerance in Multiprocessor Systems without Dedicated Redundancy”, IEEE Transactions on Computers, vol. 37, pp. 385-362, March 1988.Google Scholar
  37. 37.
    D. K. Pradhan and N. H. Vaidya, “Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture”, IEEE Transactions on Computers, vol. 43, pp. 1163-1174, October 1994.MATHCrossRefGoogle Scholar
  38. 38.
    A. Dahbura, K. Sabnani and W. Henry, “Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems”, IEEE Transactions on Computers, vol. 38, n. 6, pp. 881-891, June 1989.CrossRefGoogle Scholar
  39. 39.
    S. Tridandapani, A. K. Somani and U. R. Sandadi, “Low Overhead Multiprocessor Allocation Strategies Exploiting System Spare Capacity for Fault Detection and Location”, IEEE Transactions on Computers, vol. 44, pp. 865-877, July 1995.MATHCrossRefGoogle Scholar
  40. 40.
    M. A. Gomaa, C. Scarbrough, T. N. Vijaykumar and I. Pomeranz, “TransientFault Recovery for Chip Multiprocessors”, IEEE Micro, vol. 23, n. 6, pp. 76-83, November/December 2003.CrossRefGoogle Scholar
  41. 41.
    G. Manimaran and C. S. R. Murthy, “A Fault-Tolerant Dynamic Scheduling Algorithm for Multiprocessor Real-Time Systems and Its Analysis”, IEEE Transactions on Parallel and Distributed Systems, vol. 9, pp. 1137-1152, November 1998.CrossRefGoogle Scholar
  42. 42.
    B. Izadi and F. Ozguner, “Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor”, IEEE Transactions on Computers, vol. 52, n. 11, pp. 1443-1453, November 2003.CrossRefGoogle Scholar
  43. 43.
    A. DeHon, “Nanowire-Based Programmable Architectures”, ACM JETC, vol. 1, n. 2, pp. 109-162, 2005.CrossRefMathSciNetGoogle Scholar
  44. 44.
    R. B. Blahut, Algebraic Codes for Data Transmission, Cambridge University Press, Cambridge, 2002.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • W. Rao
    • 1
  • A. Orailoglu
    • 1
  • R. Karri
  1. 1.University of CaliforniaSan Diego

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