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Part of the book series: Series on Integrated Circuits and Systems ((ICIR))

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SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, is still computationally intensive, requiring large memory and time. Even with the many enhancements discussed in Chapter 5, sometimes the memory limitation of a single server, rather than time, can become a bottleneck for doing deeper BMC search on large designs. The main limitation of a standard BMC application is that it can perform search up to a maximum depth allowed by the physical memory on a single server. This limitation stems from the fact that as the search bound k becomes large, the memory requirement due to unrolling of the design also increases. Especially for memory-bound designs, a single server can quickly become a bottleneck in doing deeper search for bugs.

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© 2007 Springer Science+Business Media, LLC

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(2007). Distributed SAT-Based BMC. In: SAT-Based Scalable Formal Verification Solutions. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-69167-1_6

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  • DOI: https://doi.org/10.1007/978-0-387-69167-1_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-69166-4

  • Online ISBN: 978-0-387-69167-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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