Abstract
The use of hierarchy on writing algorithmic descriptions of digital systems allows the implementation of more complex designs since it increases designer’s productivity by introducing important features such as modularity, encapsulation and reusability. We are particularly interested in the problem of generating an optimal register transfer logic structure from a hierarchical algorithmic description. It is relatively straightforward to use High Level Synthesis (HLS) tools for producing an implementation from hierarchical algorithmic descriptions; each algorithmic partition is implemented separately and then linked in a following step. In general, the results are sub-optimal due to the large gap existing between the specification and implementation. In this article, we detail a simple architectural model for hierarchical algorithmic descriptions and a set of architectural transformations, which are the core of a methodology, Recursive High Level Synthesis (RHLS), aimed to optimise hierarchical implementations. The transformations are used to reshape the architecture of pre-existing hierarchical algorithmic descriptions in order to provide better synthesis results from HLS. We have implemented a suitable data structure and a set of transformations and tested them over a set of hierarchical algorithmic examples.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Teruya, M.Y., Strum, M., Chau, W.J. (2000). Architectural Transformations for Hierarchical Algorithmic Descriptions. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_42
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DOI: https://doi.org/10.1007/978-0-387-35498-9_42
Publisher Name: Springer, Boston, MA
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