Abstract
This paper presents a review of existing defect level models and introduces a new defect level model that accounts for the fault clustering effect. The model uses generalized negative binomial statistics to model the probability distribution of the number of faults in a chip. This analysis shows that clustering, in addition to naturally increasing the yield, also raises the detection probability and therefore lowers the defect level. By accounting for clustering, the new model predicts a less stringent fault coverage requirement than other models.
Work done while at Bell Labs, Murray Hill, NJ
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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Abbreviations
- α:
-
fault clustering parameter
- >αd :
-
defect clustering parameter
- λ:
-
acerage number of faults per chip
- λd :
-
acerage number of defects per chip
- Ω:
-
fault coverage
- Ωmax :
-
maximum attainable fault coverage
- Đ:
-
fault average area density
- DL :
-
defect level
- R :
-
realistic to stuck-at fault detectability ratio
- T :
-
stuck-at fault coverage
- Y :
-
true yield
- Y m :
-
measuted yield
- n0 :
-
measured yield
- r:
-
number of faults in a circuit
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© 2000 IFIP International Federation for Information Processing
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de Sousa, J.T. (2000). On Defect Level Estimation and the Clustering Effect. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_23
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DOI: https://doi.org/10.1007/978-0-387-35498-9_23
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