Abstract
We present a BDD-based algorithm for logic functions’ decomposition that is aimed at speed-up of circuits constructed as straightforward mapping of BDDs. Existing algorithms (including BDD-based) aimed at circuits’ size optimization do not solve this problem. We propose a novel decomposition formula; BDDs’ graphical properties are explicitly used. This allows to reduce circuits’ performance sufficiently. A class of BDDs occurring in arithmetic units’ synthesis is described for which the algorithm can be applied iteratively.
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© 1995 IFIP International Federation for Information Processing
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Kornilov, A.I., Isaeva, T.Y. (1995). Circuit depth optimization by BDD based function decomposition. In: Saucier, G., Mignotte, A. (eds) Logic and Architecture Synthesis. IFIP Advances in Information and Communication Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-34920-6_6
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DOI: https://doi.org/10.1007/978-0-387-34920-6_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-5041-2923-7
Online ISBN: 978-0-387-34920-6
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