Abstract
Embedded high performance computing is being called upon to provide critical computing resources with increasing frequency. The ability to tolerate faults during operation, both maintaining operational capability and ensuring that correct results continue to be produced, is an important ingredient in mission-critical systems. An architecture for such a system is proposed, providing the ability to withstand faults with graceful degradation in performance and complete transparency to the applications programmer. The final system will be able to offer fault-tolerant computing transparently to MPI applications and draws heavily on existing, demonstrated successes.
This work was funded in part by NSF Grant No. EEC-8907070 Amendment 021 and by ONR Grant No. N00014-97-1-0116.
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Dr. Samuel H. Russ, Brad Meyers, Chun-Heong Tan, and Bjorn Heckel, “UserTransparent Run-time Performance Optimization”, 2nd International Workshop on Embedded High Performance Computing, associated with IPPS '97, Geneva, Switzerland, April 1997.
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© 1998 Springer-Verlag Berlin Heidelberg
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Russ, S.H. (1998). An architecture for rapid distributed fault tolerance. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_757
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DOI: https://doi.org/10.1007/3-540-64359-1_757
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