Parallel and Distributed Processing

1. Front Matter

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2. Dynamic reconfiguration of a PMMLA for high-throughput applications

   • Gautam Ghare, Soo-Young Lee

   Pages 1-6

3. Virtual FPGAs: Some steps behind the physical barriers

   • William Fornaciari, Vincenzo Piuri

   Pages 7-12

4. A parallel algorithm for minimum cost path computation on polymorphic processor array

   • P. Baglietto, M. Maersca, M. Migliardi

   Pages 13-18

5. A performance modeling and analysis environment for reconfigurable computers

   • Jeffrey Walrath, Ranga Vemuri

   Pages 19-24

6. Runtime reconfigurable routing

   • Gordon Brebner, Adam Donlin

   Pages 25-30

7. An integrated partitioning and synthesis system for dynamically reconfigurable Multi-FPGA architectures

   • Iyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri

   Pages 31-36

8. Temporal partitioning for partially-reconfigurable-field-programmable gate

   • John Spillane, Henry Owen

   Pages 37-42

9. A Java development and runtime environment for reconfigurable computing

   • Don Davis, Michael Barr, Toby Bennett, Stephen Edwards, Jonathan Harris, Ian Miller et al.

   Pages 43-48

10. Synthesizing reconfigurable sequential machines using Tabular models

    • Kamlesh Rath, Jian Li

    Pages 49-54

11. Evaluation of a low-power reconfigurable DSP architecture

    • Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, Jan Rabaey

    Pages 55-60

12. A reconfigurable hardware-monitor for communication analysis in distributed real-time systems

    • Andreas Kirschbaum, Jürgen Becker, Manfred Glesner

    Pages 61-66

13. On reconfgurable co-processing units

    • Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

    Pages 67-72

14. A mathematical benefit analysis of context switching reconfigurable computing

    • Stephen M. Scalera, John J. Murray, Steve Lease

    Pages 73-78

15. A configurable computing approach towards real-time target tracking

    • Bharadwaj Pudipeddi, A. Lynn Abbott, Peter M. Athanas

    Pages 79-84

16. HOSMII: A virtual hardware integrated with DRAM

    • Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano

    Pages 85-90

17. Hardware reconfigurable neural networks

    • Jean-Luc Beuchat, Jacques-Olivier Haenni, Eduardo Sanchez

    Pages 91-98

18. A simulator for the reconfigurable mesh architecture

    • Carsten Steckel, Martin Middendorf, Hossam ElGindy, Hartmut Schmeck

    Pages 99-104

19. PACE: Processor architectures for circuit emulation

    • Reiner Kolla, Oliver Springauf

    Pages 105-110

20. Multiparadigm, multilingual interoperability: Experience with converse

    • L. V. Kalé, Milind Bhandarkar, Robert Brunner, Joshua Yelon

    Pages 111-122

This book constitutes the refereed proceedings of 10 international workshops held in conjunction with the merged 1998 IPPS/SPDP symposia, held in Orlando, Florida, US in March/April 1998. The volume comprises 118 revised full papers presenting cutting-edge research or work in progress.
In accordance with the workshops covered, the papers are organized in topical sections on reconfigurable architectures, run-time systems for parallel programming, biologically inspired solutions to parallel processing problems, randomized parallel computing, solving combinatorial optimization problems in parallel, PC based networks of workstations, fault-tolerant parallel and distributed systems, formal methods for parallel programming, embedded HPC systems and applications, and parallel and distributed real-time systems.

• Concurrency
• Parallel Algorithms
• Parallel Architectures
• Parallel Computing
• combinatorial optimization
• distributed computing
• distributed systems
• formal method
• formal methods
• network
• optimization
• parallel processing
• parallel programming
• programm

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