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On reconfgurable co-processing units

  • Reconfigurable Architectures Workshop Peter M. Athanas, Virginia Tech, USA Reiner W. Hartenstein, University of Kaiserslautern, Germany
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  • First Online:
Parallel and Distributed Processing (IPPS 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1388))

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Abstract

In the last years reconfigurable computing grew from a niche application to an important R&D scene. But also today most architectures lack essential features for the convenient use as a co-processing unit. E.g. embedded accelerator design with traditional FPGAs is very similar to sophisticated ASIC-design due to the bit-level granularity of FPGAs. In this paper important topics for reconfigurable platforms in multitasking systems are discussed. Run-time programmability as well as rapid application implementation using high-level languages are illustrated. Besides the underlying concepts the hardware implementation of a field-programmable ALU array (FPAA), the KrAA-III, is explained.

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References

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Authors and Affiliations

  1. University of Kaiserslautern, Erwin-Schrödinger-Straße, D-67663, Kaiserslautern, Germany

    Michael Herz, Thomas Hoffmann & Ulrich Nageldinger

Authors
  1. Reiner W. Hartenstein
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  2. Michael Herz
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  3. Thomas Hoffmann
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  4. Ulrich Nageldinger
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Editor information

José Rolim

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© 1998 Springer-Verlag Berlin Heidelberg

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Hartenstein, R.W., Herz, M., Hoffmann, T., Nageldinger, U. (1998). On reconfgurable co-processing units. In: Rolim, J. (eds) Parallel and Distributed Processing. IPPS 1998. Lecture Notes in Computer Science, vol 1388. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-64359-1_675

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  • DOI: https://doi.org/10.1007/3-540-64359-1_675

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64359-3

  • Online ISBN: 978-3-540-69756-5

  • eBook Packages: Springer Book Archive

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