Abstract
Based on a concept of equivalent capacitance, previously developed, we present a novel analytical linear representation of internal power dissipation components in CMOS structures. An extension to gates is proposed using an equivalent inverter representation, deduced from the evaluation of an equivalent transistor for serial transistors arrays. Validation of this model is given by comparing the calculated results to the simulated values (using foundries model card), with different design conditions, implemented in 0.25μm and 0.18μm CMOS processes. Application is given to delay and power optimisation of buffer and path.
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Maurine, P., Rezzoug, M., Auvergne, D. (2000). Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_13
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DOI: https://doi.org/10.1007/3-540-45373-3_13
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