Integrated Circuit Design

Power and Timing Modeling, Optimization and Simulation 10th International Workshop,PATMOS 2000 Göttingen, Germany, September 13–15, 2000 Proceedings

  • Dimitrios Soudris
  • Peter Pirsch
  • Erich Barke

Part of the Lecture Notes in Computer Science book series (LNCS, volume 1918)

Table of contents

  1. Front Matter
    Pages I-XII
  2. Opening

    1. Rene van Leuken, Reinder Nouta, Alexander de Graaf
      Pages 1-2
  3. RTL Power Modeling

    1. Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon
      Pages 3-13
    2. Alessandro Bogliolo, Enrico Macii, Virgil Mihailovici, Massimo Poncino
      Pages 14-23
    3. Gerd Jochens, Lars Kruse, Eike Schmidt, Ansgar Stammermann, Wolfgang Nebel
      Pages 24-35
    4. Crina Anton, Alessandro Bogliolo, Pierluigi Civera, Ionel Colonescu, Enrico Macii, Massimo Poncino
      Pages 36-46
  4. Power Estimation and Optimization

    1. N.D. Zervas, S. Theoharis, A.P. Kakaroudas, D. Soudris, G. Theodoridis, C.E. Goutis
      Pages 47-55
    2. Claudia Kretzschmar, Robert Siegmund, Dietmar Müller
      Pages 66-75
    3. G. Theodoridis, S. Theoharis, N.D. Zervas, C.E. Goutis
      Pages 76-87
  5. System-Level Design

    1. Mary Jane Irwin, Mahmut Kandemir, N. Vijaykrishnan, Anand Sivasubramaniam
      Pages 88-107
    2. M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
      Pages 108-117
  6. Transistor-Level Modeling

    1. Henrik Eriksson, Per Larsson-Edefors
      Pages 139-148
    2. Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
      Pages 149-158
    3. M. Rezzoug, P. Maurine, D. Auvergne
      Pages 159-167
  7. Asynchronous Circuit Design

    1. N. Starodoubtsev, A. Bystrov, A. Yakovlev
      Pages 168-177
    2. Francesco Pessolano, Joep WL Kessels
      Pages 178-186
    3. A. P. Kakaroudas, K. Papadomanolakis, V. Kokkinos, C. E. Goutis
      Pages 187-194

About these proceedings


CAD Design Circuit Design Computer Low Power Modeling and Synthesis Optimization Performance Analysis Processor Architectures Simulation Timing Design architecture logic model modeling verification

Editors and affiliations

  • Dimitrios Soudris
    • 1
  • Peter Pirsch
    • 2
  • Erich Barke
    • 3
  1. 1.Dept.of Electrical & Computer EngineeringDemocritus University of ThraceXanthiGreece
  2. 2.Institute for Communication Theory and Signal ProcessingUniversity of HanoverHanoverGermany
  3. 3.Institute for Microelectronic SystemsUniversity of HanoverHanoverGermany

Bibliographic information

  • DOI
  • Copyright Information Springer-Verlag Berlin Heidelberg 2000
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-41068-3
  • Online ISBN 978-3-540-45373-4
  • Series Print ISSN 0302-9743
  • About this book
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