Abstract
We present a logical framework for the verification of synchronous networks in an assert-commit style. It is based on the known observation that the Hoare rule for sequential composition is sound and complete for parallel composition as well. The calculus we develop inside the framework is extremely simple, based on just one propositional tautology. Nevertheless, it is powerful enough to analyze the common proof strategies (monolithic, forward and backward) applied in automated verification of such networks. This analysis leads to an incremental verification method, based on successive construction of the weakest preconditions, in which the backward proof is driven by the property being verified. In the case of finite synchronous networks this construction can be carried out via simple manipulations on circuits, and circuit optimizers can be used incrementally to simplify the complexity of such backward proofs. The method should hopefully be applicable in verification of software synchronous systems, since the current compilers for synchronous languages generate quite redundant circuits.
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Holenderski, L. (2000). Compositional Verification of Synchronous Networks. In: Joseph, M. (eds) Formal Techniques in Real-Time and Fault-Tolerant Systems. FTRTFT 2000. Lecture Notes in Computer Science, vol 1926. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45352-0_18
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DOI: https://doi.org/10.1007/3-540-45352-0_18
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