Abstract
We propose a schedule named Low Power Heterogeneous Makespan (LPHM) that attempts to minimize makespan as well as power consumption in the execution of any directed acyclic task graph on heterogeneous processors. We combine the techniques of Heterogeneous Earliest Finish Time (HEFT) [9] and voltage scaling [4]. The processors used for execution are considered to be continuously voltage scalable within the range of operation. After initial scheduling for minimum makespan, the processors are voltage scaled down to reduce power consumption whenever there is an idle time. This voltage scaling is performed without violating the precedence relationships among tasks. The simulation results show power savings of 22% over HEFT with no increase in makespan.
This work was supported in part by a grant from the National Science Foundation CCF 0411540.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Baskiyar, S., Dickinson, C.: Scheduling directed a-cyclic task graphs on a bounded set of heterogeneous processors, using task duplication. J. Parallel Distrib. Comput. Elsevier 8, 911–921 (2005)
Chandrakasan, M., Potkonjak, R., Mehra, J., Rabaey, R., Brodersen, W.: Optimizing power using transformations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 1, 12–31 (1995)
Huizer, C.M.: Power dissipation analysis of CMOS VLSI circuits by means of switch level simulation. In: IEEE European Solid State Circuits Conference, Grenoble, France, pp. 61–64 (1990)
Ishihara, T., Yasuura, H.: Voltage scheduling problem for dynamically variable voltage processors. In: Proceedings of 1998 International Symposium on Low Power Electronics and Design, pp. 197–202 (1998)
Luo, J., Jha, N.: Static and dynamic variable voltage scheduling algorithms for real-time heterogeneous distributed embedded systems. In: Proceedings of the 15th International Conference on VLSI Design, pp. 719–726 (2002)
Pouwelse, J., Langandoen, K., Sips, H.: Dynamic voltage scaling on a low-power microprocessor. UbiCom TechnicalReport 3 (2000), At: http://www.ubicom.tudelft.nl/docs/UbiCom-TechnicalReport_2000_3.PDF
Ranaweera, S., Agrawal, D.P.: A scalable task duplication based scheduling algorithm for heterogeneous systems. In: Proceedings of International Conference on Parallel Processing, pp. 383–390 (2000)
Sha, E., Zhuge, Q., Zhang, Y.: Algorithms and Analysis of Scheduling for Low-Power High-Performance DSP on VLIW Processors. International Journal of High Performance Computing and Networking 1, 3–16 (2004)
Topcuoglu, H., Hariri, S., Wu, M.-Y.: Performance-effective and low-complexity task scheduling for heterogeneous computing. IEEE TPDS 13(3), 260–274 (2002)
Palli, K.: Scheduling DAGs for Minimum Finish Time and Power Consumption on Hetero-geneous Processors: MS Thesis, Auburn University, Auburn, AL (2005)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Baskiyar, S., Palli, K.K. (2006). Low Power Scheduling of DAGs to Minimize Finish Times. In: Robert, Y., Parashar, M., Badrinath, R., Prasanna, V.K. (eds) High Performance Computing - HiPC 2006. HiPC 2006. Lecture Notes in Computer Science, vol 4297. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11945918_36
Download citation
DOI: https://doi.org/10.1007/11945918_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-68039-0
Online ISBN: 978-3-540-68040-6
eBook Packages: Computer ScienceComputer Science (R0)