Abstract
The onset of Deep Sub Micron (DSM) technology has driven the computing world towards billion device multi-GHz processor architectures leading to a stiff upward curve in power consumption and power density (W/cm 2). In this paper we develop a graph-based power model for multiprocessors that predicts power requirements across the components of the cluster (Compute node, Memory and Network system) at various hierarchical levels when applications are run. PASCOM proposes new metrics for power measurement that integrates execution module characteristics with power dissipation metrics. The PASCOM model is applied to Memory In Processor chip and we study power consumption for parallel scientific applications from SPLASH2 and NAS Parallel suite. Total power dissipated varies by 15%. However, the static and dynamic power dissipation exhibit up to 33% and 60% variation respectively due to workload characteristics.
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References
Borkar, S.: Getting Gigascale Chips. ACM Queue magazine (October 2003)
Sylvester, D., Keutzer, K.: Getting to the bottom of deep submicron. In: Proc. of International Conference on Computer-Aided Design (1998)
Vittal, A., Marek-Sadowska, M.: Low-power buffered clock tree design. IEEE Transactions on Computer-Aided Design 16, 965–975 (1997)
Gowan, M.K., Biro, L.L., Jackson, D.B.: Power considerations in the design of the Alpha 21264 microprocessor. In: Proc. of Design Automation Conference, pp. 726–731 (1998)
Petrini, F., Kerbyson, D.J., Pakin, S.: The Case of the Missing Supercomputer Performance: Achieving Optimal Performance on the 8,192 Processors of ASCI Q. In: Proceedings of Supercomputing Conference, Los Alamos National Laboratory. ACM, New York (2003)
Feng, W.C.: Making a Case for Efficient Supercomputing. ACM Queue (October 2003)
Venkateswaran, N., Shriraman, A., Krishnan, A., Niranjan, S., Srinivas, S.: Memory In Processor: Evolution of a novel Supercomputer Architecture. In: MEDEA Workshop PACT. IEEE and ACM SIGARCH (September 2003)
Venkateswaran, N., Krishnan, A., Niranjan, S., Shriraman, A., Srinivas, S.: Memory In Processor: A novel design paradigm for Supercomputers. In: ACM SIGARCH Computer Architecture News (June 2004)
Venkateswaran, N., Shriraman, A., Niranjan Kumar, S.: Memory In Processor: A novel design paradigm for Supercomputers. In: Workshop On Massively Parallel Processing (WMPP), IPDPS (April 2005)
Synopsys Corporation. Powermill Data Sheet (1999)
Mentor Graphics Corporation. Quickpower-Power estimation tool (1999)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: Proc. of the 27th International Symposium on Computer Architecture, pp. 83–94 (June 2000)
Shriraman, A., Venkateswaran, N.: Power-Delay product for Instruction Execution in a Processor, WARF Technical Report VTR_13 (November 2003), Link: http://www.cs.rochester.edu/u/ashriram/pdip.pdf
Sakurai, T.: Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI’s. IEEE Transactions on Electron Devices 40, 118–124 (1993)
Zimmermann, R., Fichtner, W.: Low-power logic styles: CMOS versus pass-transistor logic. IEEE Journal of Solid-State Circuits (1997)
Shriraman, A.: CAP: CAche Power estimator, WARF Technical Report VTR_14 (November 2003)
Industry Consortium. International Roadmap for Semiconductors (2003)
Eble III, J.C.: A Generic System Simulator with Novel On-Chip Cache and Throughput Models for Gigascale Integration, Ph.D. Dissertation, Georgia Institute of Technology, Atlanta, Georgia (1998)
Benini, L., Favalli, M., Olivo, P., Ricco, B.: A novel approach to cost-effective estimate of power disipation in CMOS ICs. In: European Design Automation Conference, pp. 354–360 (1993)
Dresig, F., Lanches, P., Rettig, O., Baitinger, U.G.: Simulation and reduction of CMOS power dissipation at logic level. In: European Design Automation Conference, pp. 341–346 (1993)
Landman, P., Rabaey, J.: Black-Box Capacitance Models for Architectural Power Analysis. In: Proceedings of the 1994 International Workshop on Low Power Design, Napa Valley, CA, pp. 165–170 (April 1994)
Chandrakasan, A.P., et al.: HYPER-LP: A System for Power Minimization Using Architectural Transformations. In: Proc. ICCAD, pp. 300–303 (November 1992)
Landman, P., Rabaey, J.: Power Estimation for High Level Synthesis. In: Proc. of EDAC-EUROASIC, pp. 361–366 (February 1993)
Davis, J.A., Meindl, J.D., De, V.K.: A Stochastic Wire-Length Distribution for Gigascale Integration (GSI). IEEE Transactions on Electron Devices 45 (March 1998)
Davis, J.A., Meindl, J.D., Zarkesh, P.: Prediction of Net Length Distribution for Global Interconnects. IEEE Transactions on VLSI (December 2000)
Stoobandt, D., Van Campenhout, J.: Accurate interconnect length estimation for predictions early in design cycle. Dept. of Electronics and Information Systems, University of Ghent-Belgium (2000)
Wilton, S., Jouppi, N.: An enhanced access and cycle time model for on-chip caches, DEC Western Research Lab Technical Report 93/5 (July 1994)
Tam, E.S., et al.: Mlcache: A Flexible Multi-Lateral Cache Simulator. In: International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 19–26 (July 1998)
Wada, T., Rajan, S., Przybylski, S.A.: An Analytical Access Time Model for On-chip Cache Memories. IEEE Journal of Solid-State Circuits 27, 1147–1156 (1992)
Zhang, M., Asanovic, K.: Highly-associative caches for low-power processors. In: Kool Chips Workshop, 33rd International Symposium on Microarchitecture (December 2000)
Bailey, D.H., Barszcz, E., et al.: The Nas Parallel Benchmarks. Intl. Journal of Supercomputer Applications 5(3), 66–73 (Fall 1991)
Culler, D.E., Singh, J.P., Gupta, A.: Parallel Computer Architecture. Morgan Kaufmann Publishers Inc., San Francisco (1999)
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Shriraman, A., Venkateswaran, N., Soundararajan, N. (2006). PASCOM: Power Model for Supercomputers. In: Grass, W., Sick, B., Waldschmidt, K. (eds) Architecture of Computing Systems - ARCS 2006. ARCS 2006. Lecture Notes in Computer Science, vol 3894. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11682127_23
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DOI: https://doi.org/10.1007/11682127_23
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