Skip to main content

Reducing Substrate Bounce in CMOS RF-Circuitry

On the use of guard rings

  • Chapter
Substrate Noise Coupling in Mixed-Signal ASICs
  • 330 Accesses

Abstract

We will discuss the use of guard rings as a mean to reduce the effects of substrate bounce in a mixed-signal IC. Measurements have been performed on lightly and heavily doped substrates in several CMOS technologies. Furthermore, we will show some of the problems of substrate bounce in RF applications where the substrate bounce is caused by digital circuitry.

Philips Research Laboratories

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Felder and J. Ganger, “Analysis of Groud-Bounce Induced Substrate Noise Coupling in a Low Resistive Bulk Epitaxial Process: Design Strategies to Minimize Noise Effects on a Mixed-Signal Chip,” IEEE Journal of Solid-State Circuits, vol. 34,no.l 1 pp. 1427–1436, Nov. 1999.

    Google Scholar 

  2. B. Nauta and G. Hoogzaad, “Substrate Bounce in Mixed-mode CMOS ICs,” in workshop on Advances in Analog Circuit Design (AACD), 1998.

    Google Scholar 

  3. D.W.J. Groeneveld, “Ground bounce in CMOS,” in workshop on Advances in Analog Circuit Design (AACD), 1993.

    Google Scholar 

  4. D. Leenaerts, P. de Vreede, “Influences of Substrate Noise on RF Performance,” European Solid-State Circuits Conf. (ESSCIRC), 2000, pp. 300–303.

    Google Scholar 

  5. D.K. Su, et.al. ‘Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits’, IEEE Journal of Solid-State Circuits, vol. 28,no.4 pp. 420–430, April. 1993.

    Article  Google Scholar 

  6. D. Leenaerts, J. van der Tang, C. Vaucher, Circuit Design for RF Transceivers, Kluwer Academic Publishers, Dordrecht, 2001.

    Google Scholar 

  7. M. van Heijningen, et.al. ‘Modeling of Digital Substrate Noise Generation and Experimental Verification Using a Novel substrate Noise Sensor’, proc. ESSCIRC’99, pp. 186–189, 1999 Duisburg.

    Google Scholar 

  8. X. Aragonès, A. Rubio, “Experimental Comparison of Substrate Noise Coupling Using Different Wafer Types,” IEEE Journal of Solid-State Circuits, vol. 34,no.10 pp. 1405–1409, Oct. 1999.

    Article  Google Scholar 

Download references

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Kluwer Academic Publishers

About this chapter

Cite this chapter

Leenaerts, D.M.W. (2004). Reducing Substrate Bounce in CMOS RF-Circuitry. In: Donnay, S., Gielen, G. (eds) Substrate Noise Coupling in Mixed-Signal ASICs. Springer, Boston, MA. https://doi.org/10.1007/0-306-48170-7_13

Download citation

  • DOI: https://doi.org/10.1007/0-306-48170-7_13

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7381-6

  • Online ISBN: 978-0-306-48170-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics