Abstract
Techniques for reducing power consumption and bandwidth limitations of inter-chip communication have been getting more attention to improve the performance of modern digital systems. This chapter begins with a brief overview of high-speed link design and describes some of the power vs. performance trade-offs associated with various design choices. The chapter then investigates various techniques that a designer may employ to reduce power consumption. Three examples of link designs and link building blocks found in the literature present energy-efficient implementations of these techniques.
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Wei, GY., Horowitz, M., Kim, J. (2002). Energy-Efficient Design of High-Speed Links. In: Pedram, M., Rabaey, J.M. (eds) Power Aware Design Methodologies. Springer, Boston, MA. https://doi.org/10.1007/0-306-48139-1_8
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DOI: https://doi.org/10.1007/0-306-48139-1_8
Publisher Name: Springer, Boston, MA
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