Power Aware Design Methodologies

  • Massoud Pedram
  • Jan M. Rabaey

Table of contents

  1. Front Matter
    Pages i-xx
  2. Massoud Pedram, Jan Rabaey
    Pages 1-8
  3. Yukihito Oowaki, Tohru Tanzawa
    Pages 51-89
  4. Tadahiro Kuroda
    Pages 91-120
  5. K. Uyttenhove, M. Steyaert
    Pages 121-149
  6. Hiroto Yasuura, Hiroyuki Tomiyama
    Pages 181-199
  7. Gu-Yeon Wei, Mark Horowitz, Jaeka Kim
    Pages 201-239
  8. N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin
    Pages 277-295
  9. Mani Srivastava
    Pages 297-334
  10. Rex Min, Seong-Hwan Cho, Manish Bhardwaj, Eugene Shih, Alice Wang, Anantha Chandrakasan
    Pages 335-372
  11. Farzan Fallah, Massoud Pedram
    Pages 373-412
  12. J. Rabaey, A. Abnous, H. Zhang, M. Wan, V. George, V. Prabhu
    Pages 451-472
  13. Luca Benini, Giovanni De Micheli
    Pages 473-516
  14. Back Matter
    Pages 517-521

About this book


Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.

The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.


CMOS Flip-Flop Hardware Sensor VLSI communication logic system on chip (SoC)

Editors and affiliations

  • Massoud Pedram
    • 1
  • Jan M. Rabaey
    • 2
  1. 1.University of Southern CaliforniaUSA
  2. 2.University of CaliforniaBerkeley

Bibliographic information

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