Abstract
In many VLSI (very large scale integration) chips, the power dissipation of the clocking system that includes clock distribution network and flip-flops is often the largest portion of total chip power consumption. In the near future, this portion is likely to dominate total chip power consumption due to higher clock frequency and deeper pipeline design trend. Thus it is important to reduce power consumptions in both the clock tree and flip-flops. Traditionally, two approaches have been used: 1) to reduce power consumption in the clock tree, several low-swing clock flip-flops and double-edge flip-flops have been introduced; 2) to reduce power consumption in flip-flops, conditional capture, clock-on-demand, data-transition look-ahead techniques have been developed. In this chapter these flip-flops are described with their pros and cons. Then, a circuit technique that integrates these two approaches is described along with simulation results. Finally, clock gating and logic embedding techniques are explained as powerful power saving techniques, followed by a low-power clock buffer design.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2000 update.
P. Gelsinger, “Microprocessors for the new millennium: challenges, Opportunities, and New Frontiers,” in IEEE Int. Solid-State Circuits Conf., Feb. 2001, pp. 22–25.
B. Pohlman, “Overcoming the Barriers to 10GHz Processors,” in Microprocessor Forum, Oct. 2001.
R. Bechade, R. Flaker, B. Kauffmann, A. Kenyon, C. London, S. Mahin, K. Nguyen, D. Pham, A. Roberts, S. Ventrone, and T. Voreyn “A 32 b 66 MHz 1.8 W microprocessor,” in IEEE Int. Solid-State Circuits Conf., Feb. 1994, pp. 208–209.
H. Kojima, S. Tanaka, Y. Okada, T. Hikage, F. Nakazawa, H. Matsushige, H. Miyasaka, and S. Hanamura, “A multi-cycle operational signal processing core for an adaptive equalizer,” VLSI Signal Process VI, pp. 150–158, Oct. 1993.
P. Gronowski, W. Bowhill, R. Preston, M. Gowan, and R. Allmon, “High-performance microprocessor design,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 676–686, May 1998.
C. J. Anderson, et al., “Physical design of a fourth-generation power GHz microprocessor,” in IEEE Int. Solid-State Circuits Conf., Feb. 2001, pp. 232–233.
E. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, “Flow-through latch and edge-triggered flip-flop hybrid elements,” in IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 138–139.
F. Klass, “Semi-dynamic and dynamic flip-flops with embedded Logic,” in Symp. on VLSI Circuits Digest of Technical Papers, Jun. 1998, pp. 108–109.
M. Nogawa and Y. Ohtomo, “A data-transition look-ahead dff circuit for statistical reduction in power consumption,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 702–706, May 1998.
M. Hamada, T. Terazawa, T. Higashi, S. Kitabayashi, S. Mita, Y. Watanabe, M. Ashino, H. Hara, and T. Kuroda, “Flip-flop selection technique for power-delay trade-off,” in IEEE Int. Solid-State Circuits Conf., Feb. 1999, pp. 270–271.
B. Kong, S.-S. Kim, and Y.-H. Jun, “Conditional-capture flip-flop technique for statistical power reduction,” in IEEE Int. Solid-State Circuits Conf., Feb. 2000, pp. 290–291.
N. Nedovic, and V. G. Oklobdzija, “Dynamic flip-flop with improved power,” in Proc. IEEE Int. Conf. Computer Design, Sep. 2000, pp. 323–326.
H. Kojima, S. Tanaka, and K. Sasaki, “Half-swing clocking scheme for 75% power saving in clocking circuitry,” IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 432–435, April 1995.
H. Kawaguchi and T. Sakurai, “A Reduced clock-swing flip-flop (rcsff) for 63% clock power reduction,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807–811, May 1998.
Y.-S. Kwon, I.-C. Park, and C.-M. Kyung, “A new single clock flip-flop for half-swing clocking,” IEICE Trans. Fundamentals, vol. E82-A, no. 11, pp. 2521–2526, Nov. 1999.
Gago, R. Escano, and J. Hidalgo, “Reduced Implementation of D-Type DET Flip-Flops,” IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 400–402, Mar. 1993.
R. Hossain, L. Wronski, and A. Albicki, “Low-power design using double edge triggered flip-flop,” IEEE Tran. VLSI Syst., vol. 2, no. 2, pp. 261–265, Jun. 1994.
S. Mishra, K. S. Yeo, and S. Rofail, “Altering transistor positions impact on the performance and power dissipation of dynamic latches and flip-Flops,” IEE Proc. Circuits, Devices and Syst., vol. 146, no. 5, pp. 279–284, Oct. 1999.
J. Tscanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, “comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors,” in IEEE Int. Symp. Low-Power Electronics and Design, Aug. 2001, pp. 147–152.
R. Heald, et al., “A third-generation spare v9 64-b microprocessor,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1526–1538, Nov. 2000.
Kowalczyk, et al., “The First MAJC microprocessor: a dual cpu system-on-a-chip,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1609–1616, Nov. 2001.
Gerosa, “A 2.2 W, 80 MHz superscalar RISC microprocessor,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1140–1454, Dec. 1994.
Y. Suzuki, K. Odagawa, and T. Abe, “Clocked CMOS calculator circuitry,” IEEE J. Solid-State Circuits, vol. 8, no. 6, pp. 462–469, Dec. 1973.
V. Stojanovic and V. G. Oklobdzija, “Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536–548, April 1999.
S. Heo, R. Krashinsky, and K. Asanovic, “Activity-sensitive flip-flop and latch selection for reduced energy,” in 2001 Conf. Advanced Research in VLSI, pp. 59–74.
N. Nedovic, and V. G. Oklobdzija, “hybrid latch flip-flop with Improved Power efficiency,” in Proc. IEEE Symp. Integrated Circuits and System Design, Sep. 2000, pp. 211–215.
N. Nedovic, M. Aleksic and V. G. Oklobdzija, “Conditional techniques for low power consumption flip-flops,” in Proc. IEEE Int. Conf. Electronics, Circuits and Systems, Sep. 2001, pp. 803–806.
N. Nedovic, M. Aleksic and V. G. Oklobdzija, “Timing characterization of dual-edge triggered flip-flops,” in Proc. IEEE Int. Conf. Computer Design, Sep. 2001, pp. 538–541.
C. Kim, and S.-M. Kang, “A low-swing clock double edge-triggered flip-flop,” in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2001, pp. 183–186.
D. Markovic, B. Nikolic, and R. Brodersen, “analysis and design of low-energy flip-flops,” in IEEE Int. Symp. Low-Power Electronics and Design, Aug. 2001, pp. 52–55.
J.-S. Wang, P.-H. Yang, and D. Sheng, “Design of a 3-V 300-MHz low-power 8-b % 8-b pipelined multiplier using pulse-triggered TSPC flip-flops,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 583–592, Apr. 2000.
T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar, “Scaling trends of cosmic rays induced soft errors in static latches beyond 0,18μm,” in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2001, pp. 61–62.
D. Brooks, P. Bose, S. Schuster, H. Jacobson, P. Kudva, A. Buyuktosunoglu, V. Zyuban, M. Gupta, and P. Gook, “Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors,”in IEEE Micro, vol. 20, no. 6, pp. 26–44, Nov.–Dec. 2000.
V. Adler and E. G. Friedman, “Repeater design to reduce delay and power in resistive interconnect,” in Proc. IEEE Int. Symp. Circuits and Systems, May 1997, pp. 2148–2151.
Vittal, and M. Marek-Sadowska, “Low-power buffered clock tree design,” IEEE Trans. Computer-Aided Design, vol. 16, no. 9, pp. 965–975, Sep. 1997.
P. Gronowski, “Designing high performance microprocessor,” in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1997, pp. 51–54.
M. Gowan, L. Biro, and D. Jackson, “Power considerations in the design of the Alpha 21264 Microprocessor,” in Proc. Design Automation Conf., June 1998, pp. 726–731.
C. Chu and D. F. Wong, “An efficient and optimal algorithm for simultaneous buffer and wire sizing,” IEEE Trans. Computer-Aided Design, vol. 18, no. 9, pp. 1297–1304, Sep. 1999.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Kluwer Academic Publishers
About this chapter
Cite this chapter
Kim, C., Kang, SM.S. (2002). Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip. In: Pedram, M., Rabaey, J.M. (eds) Power Aware Design Methodologies. Springer, Boston, MA. https://doi.org/10.1007/0-306-48139-1_6
Download citation
DOI: https://doi.org/10.1007/0-306-48139-1_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7152-2
Online ISBN: 978-0-306-48139-0
eBook Packages: Springer Book Archive