Summary
We have seen in this chapter how strengths may be assigned to gate outputs and assign statements, and how logic values driven at these strengths may be propagated through gates, driven on nets, and stored on trireg nets. The chapter closed with a brief discussion of the miniSim, a simulator written in the Verilog language that demonstrates how the logic strengths are combined together. Following this, the whole miniSim example was presented.
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© 2002 Kluwer Academic Publishers
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(2002). Switch Level Modeling. In: The Verillog® Hardware Description Language. Springer, Boston, MA. https://doi.org/10.1007/0-306-47666-5_10
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DOI: https://doi.org/10.1007/0-306-47666-5_10
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7089-1
Online ISBN: 978-0-306-47666-2
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