The Verillog® Hardware Description Language

  • Donald E. Thomas
  • Philip R. Moorby

Table of contents

  1. Front Matter
    Pages i-xxi
  2. Pages 35-71
  3. Pages 73-107
  4. Pages 109-142
  5. Pages 143-155
  6. Pages 157-193
  7. Pages 211-238
  8. Pages 239-250
  9. Pages 251-282
  10. Pages 283-292
  11. Back Matter
    Pages 293-381

About this book

Introduction

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Keywords

Advanced VLSI Describing digital systems Formal verification Hardware Logic design and simulation Simulating digital systems Synthesizing digital systems Thomas and Moorby Verification Verilog logic modeling

Authors and affiliations

  • Donald E. Thomas
    • 1
  • Philip R. Moorby
    • 2
  1. 1.ECE DepartmentCarnegie Mellon UniversityPittsburgh
  2. 2.Co-design Automation, Inc.USA

Bibliographic information

  • DOI https://doi.org/10.1007/b116662
  • Copyright Information Kluwer Academic Publishers 2002
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4020-7089-1
  • Online ISBN 978-0-306-47666-2
  • About this book
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