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Low-Voltage CMOS Log Companding Analog Design

  • Francisco Serra-Graells
  • Adoración Rueda
  • José L. Huertas

Part of the The International Series in Engineering and Computer Science book series (SECS, volume 733)

Table of contents

  1. Front Matter
    Pages i-xxv
  2. Pages 1-21
  3. Pages 51-78
  4. Pages 79-124
  5. Pages 125-135
  6. Pages 145-155
  7. Pages 177-182
  8. Back Matter
    Pages 183-192

About this book

Introduction

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

Keywords

ASIC CMOS Leistungsfeldeffekttransistor Modulation Topologie analog analog design field-effect transistor filtering filters integrated circuit modeling power systems system on chip (SoC) transistor

Authors and affiliations

  • Francisco Serra-Graells
    • 1
  • Adoración Rueda
    • 2
  • José L. Huertas
    • 2
  1. 1.Instituto de Microelectrónica de BarcelonaIMB-CNMSpanien
  2. 2.Instituto de Microelectrónica de Sevilla-CNMSpanien

Bibliographic information

  • DOI https://doi.org/10.1007/b105852
  • Copyright Information Springer Science + Business Media, Inc. 2003
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4020-7445-5
  • Online ISBN 978-0-306-48721-7
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site
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