Abstract
This chapter introduces new circuit techniques devoted to the generation of static I/V PTAT references. The topologies obtained can be understood as a particularization of the general design techniques proposed for amplification in Chapter 3. An integrated example is also presented as a demonstrator of the novel Log companding strategy.
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(2004). PTAT Generation. In: Low-Voltage CMOS Log Companding Analog Design. The International Series in Engineering and Computer Science, vol 733. Springer, Boston, MA. https://doi.org/10.1007/0-306-48721-7_5
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DOI: https://doi.org/10.1007/0-306-48721-7_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7445-5
Online ISBN: 978-0-306-48721-7
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