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Cryptographic Hardware and Embedded Systems - CHES 2005

7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings

  • Conference proceedings
  • © 2005

Overview

Editors:
  1. Josyula R. Rao

    1. IBM Watson Research Center, Yorktown Heights, USA

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  2. Berk Sunar

    1. Cryptography & Information Security Laboratory, WPI, Worcester, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3659)

Part of the book sub series: Security and Cryptology (LNSC)

Included in the following conference series:

Conference proceedings info: CHES 2005.

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Table of contents (32 papers)

  1. Side Channel II (EM)

    1. Security Limits for Compromising Emanations

      • Markus G. Kuhn
      Pages 265-279

    2. Security Evaluation Against Electromagnetic Analysis at Design Time

      • Huiyun Li, A. Theodore Markettos, Simon Moore
      Pages 280-292

  2. Side Channel III

    1. On Second-Order Differential Power Analysis

      • Marc Joye, Pascal Paillier, Berry Schoenmakers
      Pages 293-308

    2. Improved Higher-Order Side-Channel Attacks with FPGA Experiments

      • Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater
      Pages 309-323

  3. Trusted Computing

    1. Secure Data Management in Trusted Computing

      • Ulrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble
      Pages 324-338

  4. Hardware Attacks and Countermeasures II

    1. Data Remanence in Flash Memory Devices

      • Sergei Skorobogatov
      Pages 339-353

    2. Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment

      • Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont et al.
      Pages 354-365

  5. Hardware Attacks and Countermeasures III

    1. DPA Leakage Models for CMOS Logic Circuits

      • Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
      Pages 366-382

    2. The “Backend Duplication” Method

      • Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
      Pages 383-397

  6. Efficient Hardware I

    1. Hardware Acceleration of the Tate Pairing in Characteristic Three

      • P. Grabher, D. Page
      Pages 398-411

    2. Efficient Hardware for the Tate Pairing Calculation in Characteristic Three

      • T. Kerins, W. P. Marnane, E. M. Popovici, P. S. L. M. Barreto
      Pages 412-426

  7. Efficient Hardware II

    1. AES on FPGA from the Fastest to the Smallest

      • Tim Good, Mohammed Benaissa
      Pages 427-440

    2. A Very Compact S-Box for AES

      • D. Canright
      Pages 441-455

  8. Back Matter

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Other volumes

  1. Cryptographic Hardware and Embedded Systems – CHES 2005

Editors and Affiliations

  • IBM Watson Research Center, Yorktown Heights, USA

    Josyula R. Rao

  • Cryptography & Information Security Laboratory, WPI, Worcester, USA

    Berk Sunar

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