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Analyzing the Impact of Augmented Transistor NMOS Configuration on Parameters of 4x1 Multiplexer

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Abstract

This paper represents the power and delay analysis of 4×1 multiplexer based on Augmented Transistor NMOS (AT-NMOS) configurations. Transistor’s total channel width at multiple levels are considered to determine the leakage power and delay performance at 45 nm technology. It is evaluated that the performance parameter is improved in the proposed design based on Augmented Shorted Gate-Source PMOS with NMOS (ASG-S PMOS-NMOS) configuration as compared to the 4×1 multiplexer based on Static Threshold AT-NMOS (ST-ATNMOS) configuration. Using this combination, we obtain the desired performance parameters of the design. In this paper, two types of 4×1 multiplexer models are introduced. It is shown that the leakage power can be largely reduced. The delay performance is also improved up to 5% at 1 V power supply under consideration of multiple levels of transistor’s channel width due to evaluation of differentAT-NMOSconfigurations based 4×1 multiplexer models. The simulation work has been carried out using the Cadence Analog Virtuoso Spectre Simulator at 45 nm CMOS technology.

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Authors and Affiliations

  1. Malaviya National Institute of Technology, Jaipur, India

    Prateek Jain & A. M. Joshi

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  1. Prateek Jain
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  2. A. M. Joshi
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Correspondence to Prateek Jain.

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Original Russian Text © P. Jain, A.M. Joshi, 2018, published in Izvestiya Vysshikh Uchebnykh Zavedenii, Radioelektronika, 2018, Vol. 61, No. 3, pp. 163–172.

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Jain, P., Joshi, A.M. Analyzing the Impact of Augmented Transistor NMOS Configuration on Parameters of 4x1 Multiplexer. Radioelectron.Commun.Syst. 61, 121–127 (2018). https://doi.org/10.3103/S0735272718030044

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