Effect of ion implantation energy for the synthesis of Ge nanocrystals in SiN films with HfO2/SiO2 stack tunnel dielectrics for memory application
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Ge nanocrystals (Ge-NCs) embedded in SiN dielectrics with HfO2/SiO2 stack tunnel dielectrics were synthesized by utilizing low-energy (≤5 keV) ion implantation method followed by conventional thermal annealing at 800°C, the key variable being Ge+ ion implantation energy. Two different energies (3 and 5 keV) have been chosen for the evolution of Ge-NCs, which have been found to possess significant changes in structural and chemical properties of the Ge+-implanted dielectric films, and well reflected in the charge storage properties of the Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si metal-insulator-semiconductor (MIS) memory structures. No Ge-NC was detected with a lower implantation energy of 3 keV at a dose of 1.5 × 1016 cm-2, whereas a well-defined 2D-array of nearly spherical and well-separated Ge-NCs within the SiN matrix was observed for the higher-energy-implanted (5 keV) sample for the same implanted dose. The MIS memory structures implanted with 5 keV exhibits better charge storage and retention characteristics compared to the low-energy-implanted sample, indicating that the charge storage is predominantly in Ge-NCs in the memory capacitor. A significant memory window of 3.95 V has been observed under the low operating voltage of ± 6 V with good retention properties, indicating the feasibility of these stack structures for low operating voltage, non-volatile memory devices.
KeywordsHfO2 Charge Storage Memory Window Implantation Energy HREM Image
full width at half maximum
high-resolution electron microscopy
During the last decade, non-volatile memory (NVM) structures consisting of semiconductor nanocrystals (NCs), in particular, Si and Ge-NCs, embedded in a dielectric matrix have drawn considerable attraction because of their high endurance, low operating voltage, reduced lateral discharge path, low power consumption, larger retention, and faster operation [1, 2, 3, 4, 5]. Compared to Si-NC, utilization of Ge-NC as the floating gate material can give rise to enhanced device performance because of its smaller band gap, which provides both a higher confinement barrier for retention mode and a lower barrier for program/erase mode [4, 5]. Quantum confinement effects should also be higher in Ge than in Si because of its smaller electron and hole effective masses, higher dielectric constant, and larger excitonic Bohr radius [6, 7]. In recent studies, high-k gate dielectrics replaced the conventional SiO2 dielectric to be used as tunnel and control oxides in NVMs, which allows for a thinner equivalent oxide thickness without sacrificing the non-volatility [8, 9, 10, 11, 12]. Furthermore, the thicker physical thickness of the high-k dielectrics ensures good retention characteristics, while due to unique band asymmetry with Si, their lower electron barrier height allows for a larger tunneling current at low control gate voltage when the device operates in the programming regime [10, 12]. However, the trade-off between program/erase efficiency and data retention remains an important issue. One of the promising ways to improve the trade-off is to use an asymmetric tunnel barrier, which typically consists of double-stack insulating layers having different band-gap energies [13, 14, 15]. In previous studies, Wang and Lu  have implemented stacked HfO2/SiO2 tunnel layers and successfully fabricated uniform Ge-NCS with improved charge storage effect using electron-beam evaporation method. However, they have employed relatively thicker dielectric films for the evolution of Ge-NCs. In the present investigation, low-energy ion implantation method, which is fully compatible with the mainstream CMOS technology, has been employed for the formation of Ge-NCs in SiN matrix with thinner HfO2/SiO2 stack tunnel layers. In addition, taking advantage of the excellent diffusion barrier properties of Si3N4 , well-defined Ge-NCs are expected to be formed in the top nitride layer without any significant diffusion of Ge toward Si/tunnel oxide interface and/or to the surface of control layer by suitably varying the implantation parameters and annealing condition. The dependence of implantation energy for the formation and evolution of Ge-NCs in these stack structures were studied further.
Before ion implantation, 1.2 nm of SiO2 was thermally grown on p-type Si (100) substrates (resistivity 1-10 Ω cm). Subsequently, 4.7 nm of HfO2 were deposited by metal organic chemical vapor deposition technique. The top SiN layer with a thickness of about 12 nm was then deposited with electron cyclotron resonance plasma-enhanced chemical vapor deposition method under a flow of SiH4 and N2 (instead of NH3) to minimize the H content in the films. Ion implantation in these stack layers were carried out with 74Ge+ ions using GeH4 gas source for the extraction of Ge. The Ge+ ion implantation was carried out at two different energies of 3 and 5 keV, while the dose was kept constant at 1.5 × 1016 cm-2. These two sets of samples implanted at 3 and 5 keV are denoted as A3 and A5, respectively. The post-implanted samples were subjected to conventional furnace annealing at 800°C in highly pure dry N2 for 30 min for the evolution of Ge-NCs. For reference, some SiN/HfO2/SiO2 stack layers were treated under the same annealing condition without any Ge+ implantation and were defined as the control sample. The formation and evolution of Ge-NCs have been investigated using high-resolution electron microscopy (HREM) on cross-sectional specimens. Cross sectional samples were prepared by mechanical polishing and ion milling using the standard procedure. HREM images were taken using a field emission TEM (FEI Tecnai™ F20 operating at 200 kV) equipped with a spherical aberration corrector. Metal-insulator-semiconductor (MIS) memory capacitor structures were fabricated from the samples by evaporating Al electrodes with 0.8-mm diameter with a shadow mask and Al rear-side contact after scratching the back surface. Capacitance-voltage (C-V) and conductance-voltage (G-V) measurements were carried out using HP4192A impdance analyzer through a LABVIEW interface.
Results and discussion
where ΔVfb is the measured flat-band shift, Cox is the total oxide capacitance, q is the electronic charge, and A is the top contact area. The trap charge density was estimated to be 5.7 × 1012 cm-2 (sample A5) and 0.78 × 1012 cm-2 (sample A3) at a sweeping voltage of ± 7 V, indicating that the significant charge storage in sample A5 is predominantly due to Ge-NCs. It is interesting to note that the C-V curve of sample A3 shows a significant positive shift compared to the control sample, indicating the existence of fixed negative charges in the dielectrics. It is speculated that sample A3 contains a significant amount of GeO x -type network. These dangling bond structures can then capture electrons and become negatively charged, thereby causing a positive shift of the C-V curves of sample A3. Similar observations have been reported for Ge-NCs embedded in a SiO2 matrix .
In summary, we have conducted a comparative investigation of Ge+ ion implantation energy-dependent memory effects in SiN dielectric layers with HfO2/SiO2 asymmetric tunnel barriers at a constant implantation dose of 1.5 × 1016 cm-2, and subsequent thermal annealing at 800°C in N2. For the lower Ge+ implantation energy of 3 keV, no Ge-NC was observed in the stack structures, and the resultant MIS structure exhibited a small memory window of 0.74 V, which is attributed to a net negative charge storage in GeO x -dangling bonds. In contrast, for the higher Ge+ implantation energy of 5 keV, nearly spherical and well-isolated Ge-NCs with an average size of 3.5 nm were self-assembled within the top Si3N4 layer at a distance of 5.6 nm from SiN/HfO2 interface. A significant memory window of 3.95 V has been achieved over a small voltage sweep range (≤6 V). Frequency-dependent C-V and G-V curves indicate negligible contribution from interfacial defects toward the charge storage capability. An extrapolated memory window of about 1.06 V is achievable for a waiting time of 10 years due to the charge confinement in Ge-NCs, indicating the utility of these Al/SiN/Ge-NC + SiN/HfO2/SiO2/Si stack structures for low operating voltage NVM devices.
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