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AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

  • Research Article - Computer Engineering and Computer Science
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A Correction to this article was published on 10 April 2018

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Abstract

With the increase in computation and data storage in cloud servers, the need for a dedicated hardware accelerator for encryption is arising in order to reduce the processor job. High-throughput and resource-optimized implementation of 128-bit Advanced Encryption Standard (AES 128-bit), which can be used as an accelerator, is presented in this article. Memory partitioning is done in order to assign multiple ports for parallel data access. After the algorithm is pipelined and unrolled at each operation on the basis of the analyzed latency and initiation interval of different operations, for each critical path delays, a new multistage single initiation interval sub-pipelined architecture is proposed to make the initiation interval to one for lowest path delay. As a result, all operations in AES can be initiated within one clock cycle and can accept input in every clock cycle. The proposed method when simulated, synthesized, and implemented on the latest XC7VX690T device gives a throughput of 104.06 Gbps at a maximum frequency of 813 MHz and 1.23-ns path delay. The resource utilization is lower when compared with other counterparts. The proposed system gives 30.74 Mbps efficiency on XC5VLX85 device, which is 27.13% more than the best efficiency reported in a previous work.

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Change history

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads “Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0”. The original article has been corrected.

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads ?Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0?. The original article has been corrected.

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads ���Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0���. The original article has been corrected.

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads ���Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0���. The original article has been corrected.

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads ���Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0���. The original article has been corrected.

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads ���Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0���. The original article has been corrected.

  • 10 April 2018

    The original version of this article unfortunately contained mistakes. Both author names were presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads ���Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0���. The original article has been corrected.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, Tamil Nadu, India

    Baby Chellam Manjith & Natarajan Ramasubramanian

Authors
  1. Baby Chellam Manjith
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  2. Natarajan Ramasubramanian
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Correspondence to Baby Chellam Manjith.

Additional information

The original version of this article was revised: Both author names had been presented in Western display order. Correct is the Eastern display order. Therefore the correct citation of this article reads “Manjith B.C. & Ramasubramanian N. Arab J Sci Eng (2017). https://doi.org/10.1007/s13369-017-2925-0”.

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Baby Chellam, M., Natarajan, R. AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency. Arab J Sci Eng 43, 6873–6890 (2018). https://doi.org/10.1007/s13369-017-2925-0

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  • DOI: https://doi.org/10.1007/s13369-017-2925-0

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