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Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation

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Abstract

Silicon Diagnosis is the process of locating potential defect sites (candidates) in a defective chip. These candidates are then used as an aid during physical failure analysis. It is desired that the cardinality of the candidate set returned by silicon diagnosis be as small as possible. To this end, effective test patterns that can distinguish as many fault-pairs in the candidate set are critical. Generation of such diagnostic patterns is referred to as Automatic Diagnostic Test Generation (ADTG). In this paper, we propose an aggressive and efficient learning framework for such a diagnostic test generation engine. It allows us to identify and prune non-trivial redundant search states thereby allowing to easily solve hard to distinguish or hard to prove equivalent fault-pairs. Further, we propose an incremental flow for ADTG, where the information learned during detection-oriented test generation is passed to and incrementally used by ADTG. Finally, we propose an interesting output deviation based X-filling of detection test patterns with the objective of enhancing test set’s diagnostic ability. Experimental results on full-scan versions of ISCAS89/ITC99 circuits indicate that our incremental learning framework achieves up to 2× speed-up and/or resolves more initially unresolved fault-pairs for most circuits. Also, results indicate that the proposed X-filling method has the potential to distinguish more fault-pairs than the random X-filling method.

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Notes

  1. \(d^{2,\overline{D}}\) is the first implication at level 2. Since we check for compatibility after each implication the gates e and f will not be implied when the compatibility occurs.

References

  1. Badereddine N et al (2006) Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics. In: Design and test of integrated systems in nanoscale technology, pp 359–364

  2. Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark designs and a special translator in fortran. In: International symposium on circuits and systems, pp 695–698

  3. Brglez F, Bryan D, Kozminski K (1989) Combinational profiles of sequential benchmark circuits. In: International symposium on circuits and systems, pp 1929–1934

  4. Camurati P et al (1990) Diagnosis oriented test pattern generation. In: European design automation conference, pp 470–474

  5. Camurati P et al (1990) A diagnostic test pattern generation algorithm. In: International test conference, pp 52–58

  6. Chandrasekar M, Hsiao M (2009) Diagnostic test generation for silicon diagnosis with an incremental learning framework based on search state compatibility. In: High level design validation and test workshop, pp 68–75

  7. Corno F, Sonza Reorda M, Squillero G (2000) RT-level ITC 99 benchmarks and first ATPG results. In: IEEE design and test of computers, vol 17(3), July–Sept, pp 44–53

  8. Giraldi J et al (1991) EST: the new frontier in ATPG. In: Design automation conference, pp 667–672

  9. Goel P (1981) An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput C-30(3):215–222

    Article  MATH  MathSciNet  Google Scholar 

  10. Gruning T et al (1991) DIATEST: a fast diagnostic test pattern generator for combinational circuits. In: International conference on computer-aided design, pp 194–197

  11. Hamzaoglu I et al (1998) New techniques for deterministic test pattern generation. In: VLSI test symposium, pp 446–452

  12. Hartanto I et al (1996) Diagnostic fault equivalence identification using redundancy information and structural analysis. In: International test conference, pp 294–302

  13. Hartanto I et al (1997) Diagnostic test pattern generation for sequential circuits. In: VLSI test symposium, pp 196–202

  14. Kavousianos X, Chakrabarty K (2009) Generation of compact test sets with high defect coverage. In: Design, automation and test in Europe, pp 1130–1135

  15. Kuehlmann A et al (2002) Robust boolean reasoning for equivalence checking and functional property verification. IEEE Trans Comput-Aided Des Integr Circuits Syst 21(12):1377–1394

    Article  Google Scholar 

  16. Li J, Liu X, Zhang Y, Hu Y, Li X, Xu Q (2008) On capture power-aware test data compression for scan-based testing. In: International conference on computer-aided design, pp 67–72

  17. Marion’s EJ, Nicolici N (2007) Editorial: silicon debug and diagnosis. IET Comp Digit Tech 1(6):659–660

    Article  Google Scholar 

  18. Marques-Silva JP, Sakallah KA (1999) GRASP: a search algorithm for propositional satisfiability. IEEE Trans Comput 48(5):506–521

    Article  MathSciNet  Google Scholar 

  19. Moskewicz M et al (2001) CHAFF: engineering an efficient SAT solver. In: Design automation conference, pp 530–535

  20. Pomeranz I et al (1998) Diagnostic test generation procedure for combinational circuits based on test elimination. In: Asian test symposium, pp 486–491

  21. Reddy SM et al (1998) Diagnostic test generation procedure for synchronous sequential circuits based on test elimination. In: International test conference, pp 1074–1083

  22. Reddy SM et al (2007) z-diagnosis: framework for diagnostic fault simulation and test generation utilizing subsets of outputs. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(9):1700–1712

    Article  Google Scholar 

  23. Roth JP (1966) Diagnosis of automata failures: a calculus and a method. IBM Journal of Research and Development 10(4):278–291

    Article  MATH  Google Scholar 

  24. Roth JP et al (1967) Programmed algorithms to compute tests to detect and distinguish between failures. IEEE Trans Electron Comput EC-16(5):567–580

    Article  Google Scholar 

  25. Savir J, Roth JP (1982) Testing for, and distinguishing between failures. In: 12th fault tolerant computing symposium, pp 165–172

  26. Silva J, Sakallah KA (1994) Dynamic search-space pruning techniques in path sensitization. In: Proceedings of design automation conference, pp 705–711

  27. Tzeng C-W, Huang S-Y (2009) QC-fill: an X-fill method for quick-and-cool scan test. In: Design, automation and test in Europe, pp 1142–1147

  28. Veneris A et al (2004) Fault equivalence and diagnostic test generation using ATPG. In: International symposium on circuits and systems, pp V-221–V-224

  29. Venkataraman S et al (1995) Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists. In: Design automation conference, pp 133–138

  30. Wang Z, Chakrabarty K (2006) An efficient test pattern selection method for improving defect coverage with reduced test data volume and test application time. In: Asian test symposium, pp 333–338

  31. Wang Z, Chakrabarty K (2008) Test-quality/cost optimization using output-deviation-based reordering of test patterns. IEEE Trans Comput-Aided Des Integr Circuits Syst 27(2):352–365

    Article  Google Scholar 

  32. Wang L-T et al (2006) VLSI test principles and architectures. Morgan Kaufmann Publishers

  33. Wang Z, Chakrabarty K, Goessel M (2006) Test set enrichment using a probabilistic fault model and the theory of output deviations. In: Design, automation and test in Europe, pp 1–6

  34. Wang Z, Fang H, Chakrabarty K, Bienek M (2009) Deviation-based LFSR reseeding for test-data compression. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(2):259–271

    Article  Google Scholar 

  35. Zhang L, Madigan C, Moskewicz M, Malik S (2001) Efficient conflict driven learning in Boolean SAT solver. In: International conference on computer-aided design, pp 279–285

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Authors and Affiliations

  1. 302 Whittemore Hall, Virginia Tech, Blacksburg, VA, 24060, USA

    Maheshwar Chandrasekar & Nikhil P. Rahagude

  2. 355 Durham Hall, Virginia Tech, Blacksburg, VA, 24060, USA

    Michael S. Hsiao

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  1. Maheshwar Chandrasekar
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  2. Nikhil P. Rahagude
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  3. Michael S. Hsiao
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Correspondence to Maheshwar Chandrasekar.

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Responsible Editor: P. Mishra

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Chandrasekar, M., Rahagude, N.P. & Hsiao, M.S. Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation . J Electron Test 26, 165–176 (2010). https://doi.org/10.1007/s10836-010-5142-2

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  • DOI: https://doi.org/10.1007/s10836-010-5142-2

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