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Journal of Electronic Testing

, Volume 24, Issue 1–3, pp 129–141 | Cite as

Performance-Optimized Design for Parametric Reliability

  • Ramyanshu Datta
  • Jacob A. Abraham
  • Abdulkadir Utku Diril
  • Abhijit Chatterjee
  • Kevin J. Nowka
Article
  • 63 Downloads

Abstract

Process variations have a significant impact on behavior of integrated circuits (ICs) designed in deep sub-micron (DSM) technologies, and it has been estimated that in some cases up to a generation of performance can be lost due to process variations (Bowman et al., IEEE J Solid State Circuits 37:183–190, 2002), making it a significant problem for design and manufacture of DSM ICs. Adaptive design techniques are fast evolving as a potential solution to this problem. Such techniques facilitate reconfiguration of an IC to enable its operation across process corners, thus ensuring parametric reliability in such ICs, and also improving manufacturing yield. In this paper, adaptive design techniques with a focus on timing of ICs, i.e., performance-optimized adaptive design, are explored. The focus of such performance-optimized adaptive design techniques is to ensure that adaptation does not cause an IC to violate timing specifications, thus giving priority to performance, which remains one of the most important parameters of an IC.

Keywords

Adaptive design Process variation compensation Noise tolerance Parametric reliability 

Notes

Acknowledgment

The authors would like to thank Antony Sebastine and Whitney J. Townsend for design of the multipliers.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Ramyanshu Datta
    • 1
  • Jacob A. Abraham
    • 1
  • Abdulkadir Utku Diril
    • 2
  • Abhijit Chatterjee
    • 3
  • Kevin J. Nowka
    • 4
  1. 1.Computer Engineering Research CenterThe University of Texas at AustinAustinUSA
  2. 2.Vivante CorporationSanta ClaraUSA
  3. 3.Georgia Institute of TechnologyAtlantaUSA
  4. 4.IBM Austin Research LaboratoryAustinUSA

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