Journal of Computational Electronics

, Volume 15, Issue 2, pp 367–380 | Cite as

Reduced thickness interconnect model using GNR to avoid crosstalk effects

  • Sandip Bhattacharya
  • Debaprasad Das
  • Hafizur Rahaman


In this research article, we propose a reduced thickness multilayer graphene nanoribbon (MLGNR) interconnect model to reduce crosstalk effects. The \(10\times \) higher current capability of MLGNR than copper (Cu) makes it an attractive choice to alleviate electromigration problem. The lower resistance of MLGNR is also an important factor to reduce interconnect delay. We have shown that a reduced thickness interconnect structure using MLGNR can reduce the crosstalk effects significantly without compromising the other benefits. The analysis is performed for side-contact GNR (SC-GNR) and top-contact GNR (TC-GNR) structure. Our analysis shows that the reduced thickness side-contact GNR interconnects can achieve \(\sim \)1.02 to \(2.36\times \) reduction in crosstalk induced delay as compared with Cu. Our analysis also shows that the top-contact GNR structure with few layers can also achieve \(\sim \)1.58 to \(1.95\times \) reduction in crosstalk induced delay as compared with Cu. We have performed crosstalk noise and overshoot/undershoot analysis using our proposed model. It is shown that the near-end and far-end crosstalk noise and overshoot/undershoot for SC-GNR and TC-GNR structures are significantly smaller than that of Cu.


Crosstalk Delay Multilayer graphene nanoribbon (MLGNR) Noise Overshoot/undershoot 


Compliance with Ethical Standards


This work is partially supported by the DIT, Government of West Bengal, India under VLSI Design Project.

Conflict of Interest

The authors declare that they have no conflict of interest.

Human Participants and/or Animals

This article does not contain any studies with human participants or animals performed by any of the authors.

Informed consent

Informed consent was obtained from all individual participants included in the study.


  1. 1.
    Bhattacharya, S., Das, D., Rahaman, H.: A novel GNR interconnect model to reduce crosstalk delay. In: Fifth International Symposium on Electronic System Design (ISED-2014), pp. 5–9 (2014)Google Scholar
  2. 2.
    International Technology Roadmap for Semiconductors (ITRS) reports. (2006)
  3. 3.
    Naeemi, A., Meindl, J.D.: Compact physics-based circuit models for graphene nanoribbon interconnects. IEEE Trans. Electron Devices 56(9), 1822–1833 (2009)CrossRefGoogle Scholar
  4. 4.
    Naeemi, A., Meindl, J.D.: Conductance modeling for graphene nanoribbon (GNR) interconnects. IEEE Electron Device Lett. 28(5), 428–431 (2007)CrossRefGoogle Scholar
  5. 5.
    Xu, C., Li, H., Banerjee, K.: Modeling, analysis, and design of graphene nano-ribbon interconnects. IEEE Trans. Electron Device 56(8), 1567–1578 (2009)CrossRefGoogle Scholar
  6. 6.
    Nasiri, S.H., Moravvej-Farshi, M.K., Faez, R.: Stability analysis in graphene nanoribbon interconnects. IEEE Electron Device Lett. 31(12), 1458–1460 (2010)CrossRefGoogle Scholar
  7. 7.
    Das, D., Rahaman, H.: Crosstalk and gate oxide reliability analysis in graphene nanoribbon interconnects. Int. Symp. Electron. Syst. Design (ISED-2011), pp. 182–187 (2011)Google Scholar
  8. 8.
    Das, D., Rahaman, H.: Modeling of IR-drop induced delay fault in CNT and GNR power distribution networks. In: 5th International Conference on Computers and Devices for Communication (CODEC 2012), pp. 1–4 (2012)Google Scholar
  9. 9.
    Das, S., Bhattacharya, S., Das, D., Rahaman, H.: RF performance analysis of graphene nanoribbon interconnect, Student’s Technology Symposium (TechSym-2014), pp. 105–110 (2014)Google Scholar
  10. 10.
    Kumar, V., Rakheja, S., Naeemi, A.: Performance and energy-per-Bit modeling of multilayer graphene nanoribbon conductors. IEEE Trans. Electron Devices 59(10), 2753–2761 (2012)CrossRefGoogle Scholar
  11. 11.
    Nandy, T., Dutta, A., Haque, M.A., Mahmood, Z.H.: High frequency compatibility of doped multilayer graphene nanoribbon in VLSI interconnect with respect to skin depth effect and layer width variation. Int. Conf. Inf. Electron. Vis. (ICIEV-2014), pp.1–5 (2014)Google Scholar
  12. 12.
    Zhao, W.-S., Yin, W.-Y.: Signal integrity analysis of graphene nano-ribbon (GNR) interconnects. In: Electrical Design of Advanced Packaging and Systems Symposium (EDAPS-2012), pp. 227–230 (2012)Google Scholar
  13. 13.
    Nishad, A.K., Sharma, R.: Analytical time-domain models for performance optimization of multilayer GNR interconnects. IEEE J. Sel. Top. Quantum Electron. 20(1), 17–24 (2014)CrossRefGoogle Scholar
  14. 14.
    Pan, C., Raghavan, P., Ceyhan, A., Catthoor, F., Tokei, Z., Naeemi, A.: Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node. IEEE Trans. Electron Devices 62(5), 1530–1536 (2015)CrossRefGoogle Scholar
  15. 15.
    Xia, F., Perebeinos, V., Lin, Y.-M., Wu, Y., Avouris, P.: The origins and limits of metal-graphene junction resistance. Nat. Nanotechnol. 6(3), 179–184 (2011)CrossRefGoogle Scholar
  16. 16.
    Leong, W.S., Gong, H., Thong, J.T.L.: Low-contact-resistance graphene devices with nickel-etched-graphene contacts. ACS Nano 8(1), 994–1001 (2014)Google Scholar
  17. 17.
    Predictive Technology Model (2008).
  18. 18.
    Chen, J.F., Tao, J., Fang, P., Chenming, H.: Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates. IEEE J. Solid-State Circ. 34(3), 367–371 (1999)CrossRefGoogle Scholar
  19. 19.
    Nagaraj, N.S., Hunter, W.R., Balsara, P., Cantrell, C.: The Impact of inductance on transients affecting gate oxide reliability. In: 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design, pp. 709–713 (2005)Google Scholar
  20. 20.
    Liao, A.D., Behnam, A., Dorgan, V.E., Zuanyi, L.i., Pop, E.: Reliability, failure, and fundamental limits of graphene and carbon nanotube interconnects. In: IEEE International Electron Devices Meeting (IEDM), pp. 15.1.1–15.1.4 (2013)Google Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Sandip Bhattacharya
    • 1
  • Debaprasad Das
    • 2
  • Hafizur Rahaman
    • 1
  1. 1.School of VLSI TechnologyIndian Institute of Engineering Science and TechnologyShibpurIndia
  2. 2.Department of Electronics and Communication EngineeringAssam UniversitySilcharIndia

Personalised recommendations