Journal of Automated Reasoning

, Volume 49, Issue 4, pp 583–619

Simulating Circuit-Level Simplifications on CNF

  • Matti Järvisalo
  • Armin Biere
  • Marijn J. H. Heule

DOI: 10.1007/s10817-011-9239-9

Cite this article as:
Järvisalo, M., Biere, A. & Heule, M.J.H. J Autom Reasoning (2012) 49: 583. doi:10.1007/s10817-011-9239-9


Boolean satisfiability (SAT) and its extensions have become a core technology in many application domains, such as planning and formal verification, and continue finding various new application domains today. The SAT-based approach divides into three steps: encoding, preprocessing, and search. It is often argued that by encoding arbitrary Boolean formulas in conjunctive normal form (CNF), structural properties of the original problem are not reflected in the CNF. This should result in the fact that CNF-level preprocessing and SAT solver techniques have an inherent disadvantage compared to related techniques applicable on the level of more structural SAT instance representations such as Boolean circuits. Motivated by this, various simplification techniques and intricate CNF encodings for circuit-level SAT instance representations have been proposed. On the other hand, based on the highly efficient CNF-level clause learning SAT solvers, there is also strong support for the claim that CNF is sufficient as an input format for SAT solvers. In this work we study the effect of CNF-level simplification techniques, focusing on SatElite-style variable elimination (VE) and what we call blocked clause elimination (BCE). We show that BCE is surprisingly effective both in theory and in practice on CNF formulas resulting from a standard CNF encoding for circuits: without explicit knowledge of the underlying circuit structure, it achieves the same level of simplification as a combination of circuit-level simplifications and previously suggested polarity-based CNF encodings. We also show that VE can achieve many of the same effects as BCE, but not all. On the other hand, it turns out that VE and BCE are indeed partially orthogonal techniques. We also study the practical effects of combining BCE and VE for reducing the size of formulas and on the running times of state-of-the-art SAT solvers. Furthermore, we address the problem of how to construct original witnesses to satisfiable CNF formulas when applying a combination of BCE and VE.


Boolean satisfiability Preprocessing Problem structure Blocked clauses Variable elimination Boolean circuits 

Copyright information

© Springer Science+Business Media B.V. 2011

Authors and Affiliations

  • Matti Järvisalo
    • 1
  • Armin Biere
    • 2
  • Marijn J. H. Heule
    • 3
  1. 1.Department of Computer ScienceUniversity of HelsinkiHelsinkiFinland
  2. 2.Institute for Formal Models and VerificationJohannes Kepler UniversityLinzAustria
  3. 3.Department of Software TechnologyDelft University of TechnologyDelftThe Netherlands

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