International Journal of Parallel Programming

, Volume 39, Issue 5, pp 639–661 | Cite as

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

  • Alper Sen
  • Baris Aksanli
  • Murat Bozkurt


Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.


Graphics processing units (GPU) Parallel logic simulation Cycle based simulation And inverter graph (AIG) 


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© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Department of Computer EngineeringBogazici UniversityIstanbulTurkey

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