# A novel two-channel continuous-time time-interleaved 3rd-order sigma-delta modulator with integrator-sharing topology

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## Abstract

This paper presents a 3rd-order two-path continuous-time time-interleaved (CTTI) delta-sigma modulator which is implemented in standard 90 nm CMOS technology. The architecture uses a novel method to resolve the delayless feedback path issue arising from the sharing of integrators between paths. By exploiting the concept of the time-interleaving techniques and through the use time domain equations, a conventional single path 3rd-order discrete-time (DT) ΔΣ modulator is converted into a corresponding two-path discrete-time time-interleaved (DTTI) counterpart. The equivalent CTTI version derived from the DTTI ΔΣ modulator by determining the DT loop filters and converting them to the equivalent continuous-time loop filters through the use of the Impulse Invariant Transformation. Sharing the integrators between two paths of the reported modulator makes it robust to path mismatch effects compared to the typical time-interleaved modulators which have individual integrators in all paths. The modulator achieves a dynamic range of 12 bits with an OverSampling Ratio of 16 over a bandwidth of 10 MHz and dissipates only 28 mW of power from a 1.8-V supply. The clock frequency of the modulator is 320 MHz but integrators, quantizers and DACs operate at 160 MHz.

## Keywords

Discrete-time Continuous-time Delta-sigma modulator Signal transfer function Noise transfer function Time-interleaved## 1 Introduction

The rapid growth of the portable communication device markets such as audio systems and consumer electronics has been led to an increasing demand for low power high resolution ADC designs over the last decade [1]. The ΔΣ modulator can achieve a very high resolution analog-to-digital conversion for relatively low-bandwidth signals through the use of the oversampling and the noise shaping technique. It is known that ΔΣ modulators do not require precise analog components and sharp cut-off frequencies for their analog anti-aliasing filters. The noise-shaping loop filter of a ΔΣ modulator can be implemented as a DT structure by using Switched-Capacitor (SC) techniques or as CT one through active-RC or gm-c filters. The SC circuits are insensitive to clock jitter and the frequency response of the noise-shaping filter can be accurately set by capacitor ratios [2].

The signal bandwidth the ΔΣ modulators can deal with is narrow and is restricted by the OSR and technology deployed. To increase the signal bandwidth the modulator can process, a variety of methods are used: the first one is to increase the order of the modulator, but at a price, where the stability problem requires to be dealt with very carefully [2]. The second is to increase the number of bits for the quantizer, which makes the design of the modulator more complicated [1]. The third is to increase the sampling frequency. However, the major disadvantage of the third method is the technology limitations. The fourth method that is one of the more practical ways is to deploy a CT loop filter coupled with the time-interleaving technique [3].

This paper is organized as follows. In Sect. 2, the CT ΔΣ modulators and the concept of the impulse-invariant transformation are reviewed. In Sect. 3, a single-path DTTI ΔΣ modulator is derived from a 3rd-order conventional DT ΔΣ modulator through the use of the time domain equations and it is converted to its equivalent CTTI ΔΣ modulator. The delayless feedback path problem and our proposed solution are both discussed in detail in this section. In Sect. 4, MATLAB simulation results are presented. In Sect. 5, circuit design and simulations are reviewed. Finally, conclusions are given in Sect. 6.

## 2 Continuous-time ΔΣ modulator

The CT ΔΣ modulators benefit from operating at higher sampling frequencies in comparison to their DT counterparts. The errors of the sample-and-hold circuit are shaped by the loop filter and the CT ΔΣ modulators have an implicit anti-aliasing filter in their forward signal path; However, CT ΔΣ modulators suffer from several drawbacks: excess loop delay, jitter sensitivity and RC time constant variations.

According to [4], the effect of “sinc” term is negligible and neglected in this work for the purpose of comparison between the CT modulator with its DT counterpart.

## 3 Time-interleaved ΔΣ modulator

The procedure for the design of a ΔΣ modulator is based on choosing: the order and architecture of the ΔΣ modulator, the OSR and the number of bits for the quantizer. By using the time-interleaving technique and M interconnected parallel modulators that are working concurrently, the effective sampling rate and the OSR become M times the clock rate and the OSR of each modulator respectively [8, 9]. It should be noted that the required resolution can be acquired without increasing the order of the modulator or the number of bits for the quantizer and also without utilizing a state of the art technology.

### 3.1 Derivation of TI ΔΣ modulator

The motive behind sharing one set of integrators is to eliminate the instability that can arise due to the DC offset mismatch of the two individual integrator set based two channel interleaving case [8, 15, 17]. The DTTI ΔΣ modulators require an input demultiplexer which samples the input signal at the highest clock frequency of the DTTI ΔΣ modulator and distributes it between channels. This fast demultiplexer is a limiting factor for the performance of the DTTI ΔΣ modulators. This architecture does not require an input demultiplexer and the input signal is shared between channels [1, 8]. Removing the input demultiplexer has no effect on the NTF of the DTTI ΔΣ modulator but it causes some notches in its STF at the following frequencies \(0.5F_{clk} , 1.5F_{clk} , 2.5F_{clk} , 3.5F_{clk} , \ldots\) which is shown in Fig. 10 where \(F_{clk}\) is the clock frequency of the DTTI ΔΣ modulator [9].

### 3.2 Delayless feedback path problem in TI ΔΣ modulator

As stated in (20), \(y_{1e} \left( n \right)\) (the output of Q1) requires to be corrected before it is applied to the input of DAC1; otherwise it causes instability in the modulator as it will change the modulators dynamics by increasing its order.

Comparison of the first, the second and the proposed method

Comparators count for \(Q_{1}\) | Comparators count for \(Q_{2}\) | Advantage | Disadvantage | |
---|---|---|---|---|

First method [11] | 48 | 16 | Less hardware required | 32 more comparators required for \(Q_{1}\) |

Second method [2] | 16 | 16 | Less comparators required | A sample-and-hold, a complicated timing generator and faster integrators required |

Proposed method | 32 | 16 | Less hardware required | 16 more comparators required for \(Q_{1}\) |

### 3.3 Derivation of continuous-time TI (CTTI) ΔΣ modulator

The OSR of the overall modulator shown in Fig. 9 from \(x\left( t \right)\) to \(y\left( n \right)\) is 16 and has been designed to operate at 320 MHz clock frequency for a 10 MHz signal bandwidth. The resolution of Q1 and Q2 are 5 and 4 bits respectively. After correcting the error as stated by Eq. (21) in the digital domain, \(y_{1} \left( n \right)\) will be 4 bits in length. Therefore, DAC1 and DAC2 both require 4 bit DACs. To simplify the design, generally, the coefficient \(c\) scaling the first order differencer \((1 - z^{ - 1} )\) in the digital domain should be chosen to be a number which is a power of two. This choice results in replacing the potentially complicated multiplier with a simple hard-wired shift.

### 3.4 STFs and NTFs of the DTTI and CTTI ΔΣ modulator

*STF*of the CTTI ΔΣ modulator \(\left( {STF_{c} \left( s \right)} \right)\), both \(NTF_{1d} \left( z \right)\) and \(NTF_{2d} \left( z \right)\) are used and the \(STF_{c} \left( s \right)\) is given in (29):

## 4 MATLAB simulation results

The specifications of the CTTI ΔΣ modulator

\(a\) | 0.27639 |

\(b\) | 0.76393 |

\(c\) | 2.00000 |

\(f_{c1}\) | 1.00000 |

\(f_{c2}\) | 1.00000 |

\(f_{c3}\) | 1.00000 |

\(f_{c4}\) | 1.27639 |

\(f_{c5}\) | 0.96480 |

\(f_{c6}\) | 1.72874 |

\(f_{c7}\) | 0.67082 |

\(f_{c8}\) | 1.32917 |

\(f_{c9}\) | 1.32917 |

\(f_{c10}\) | 2.19868 |

OSR | 16 |

Clock frequency | 320 MHz |

Signal bandwidth | 10 MHz |

DAC1 | 4-bit DAC |

DAC2 | 4-bit DAC |

Q1 | 5-bit quantizer |

Q2 | 4-bit quantizer |

Excess loop delay (intentional) | 0.25 T |

## 5 Circuit Design and Simulation

As can be seen in Fig. 15, three active-RC integrators have been used and RC time constant varies up to 50% in CMOS technologies. A tunable capacitor array will be used to tune up the RC time constant of the integrators and to compensate for process variations [12].

This modulator requires two ADCs. The first ADC has 5 bits resolution and 31 comparators and the second ADC has 4 bits resolution and 15 comparators. As shown in Fig. 16, each latched comparator is composed of a single preamplifier stage and a latch. The preamplifier is used to amplify the input signal and to minimize the input capacitance of the comparator. The preamplifier stage isolates the latch and the resistor ladder; therefore it reduces the kick-back noise seen in reference string during switching times of the comparator. The latch is used to compare the two amplified input signals coming from the preamplifier and to provide a digital rail-to-rail output signal.

The whole CTTI ΔΣ modulator has been simulated with an input frequency of \(F_{in} = 1.005\;{\text{MHz}}\), an amplitude of \(1.6V_{pp}\) (− 2 dBFS) and a sampling rate of 320 MHz across process corners and temperatures. Due to the excessive long simulation times, these circuit simulation results were obtained by using only 16,384-point FFTs. Since the signal bandwidth is 10 MHz, up to 512 frequency bins will be included in the calculation of the SNDR. The circuit-level simulations have been run to make sure that the modulator is stable across process corners and temperatures. The SNDR of the modulator obtained from circuit simulations in TT 27 °C, FF 120 °C and SS − 40 °C are 75.3, 75.9 and 74.5 dB respectively.

## 6 Conclusions

In this paper the design of a 3rd-order CTTI ΔΣ modulator with one set of integrators in the 90 nm CMOS TSMC technology has been presented. A novel method to resolve the delayless feedback path issue has been proposed, designed, implemented and tested to demonstrate the novel approach [18]. The results obtained from the circuit simulations confirm what was expected from the theory behind the proposed method and works very well without any noticeable degradation in the output performance. The designed circuit has furthermore been demonstrated in simulation to achieve a dynamic range of 12 bits with an OverSampling Ratio (OSR) of 16 over a bandwidth of 10 MHz and dissipates only 28 mW of power from a 1.8-V supply. The clock frequency of the modulator is 320 MHz but the integrators, quantizers and DACs operate at 160 MHz.

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