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Architecture and Cross-Layer Design Space Exploration

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Abstract

The task of architectural Design Space Exploration (DSE) is extremely complex, with multiple architectural parameters to be tuned and optimized, resulting in a huge design space that needs to be explored efficiently. Furthermore, each architectural parameter and/or design point is critically affected by decisions made at lower levels of abstraction (e.g., layout, choice of transistors, etc.). Ideally designers would like to perform DSE incorporating information and decisions made across multiple layers of design abstraction so that the ensuing design space is both feasible and has good fidelity. Simulation-based methods alone can not deal with this incredibly large and complex design space. To address these issues, this chapter presents an approach for cross-layer architectural DSE that efficiently prunes the large design space and furthermore uses predictive models to avoid expensive simulations. The chapter uses a single-chip heterogeneous single-ISA multiprocessor as an exemplar to demonstrate how the large search space can be covered and evaluated efficiently. A cross-layer approach is presented to cope with the complexity by restricting the search/design space through the use of cross-layer prediction models to avoid too costly full system simulations, coupled with systematic pruning of the design space to enable good coverage of the design space in an efficient manner.

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Abbreviations

CLDSE:

Cross-Layer Design Space Exploration

DoE:

Design of Experiments

DSE:

Design Space Exploration

EDP:

Energy-Delay Product

EDSP:

Energy-Delay Square Product

HMP:

Heterogeneous Multi-core Processor

ILP:

Instruction-Level Parallelism

ISA:

Instruction-Set Architecture

RSM:

Response Surface Modeling

SA:

Simulated Annealing

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Acknowledgements

This work was partially supported by the NSF Variability Expedition award CCF-1029783.

Author information

Authors and Affiliations

  1. University of California Irvine, Irvine, CA, USA

    Santanu Sarma

  2. Center for Embedded and Cyber-Physical Systems, University of California Irvine, Irvine, CA, USA

    Nikil Dutt

Authors
  1. Santanu Sarma
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  2. Nikil Dutt
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Correspondence to Santanu Sarma .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Sarma, S., Dutt, N. (2017). Architecture and Cross-Layer Design Space Exploration. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_9

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