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Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis

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Handbook of Hardware/Software Codesign

Abstract

This chapter summarizes more than 20 years of experience by the virtual prototyping group of Synopsys in the commercial deployment of Hardware/Software Codesign (HSCD). The goal of HSCD has always been to reduce time to market, increase design productivity, and improve the quality of results. From all the different facets of HSCD, virtual prototyping – complemented by links to emulation and FPGA prototyping – has so far proven to achieve the best return of investment with respect to these goals. This chapter first gives an overview of the main virtual prototyping use cases in the context of an end-to-end prototyping flow, which also includes physical prototyping and hybrid prototyping. The second part introduces the SystemC Transaction-Level Model (TLM) standard and the Unified Power Format (UPF) as the main modeling languages for the creation of Virtual Prototypes (VPs) and system-level power models. The main body of this chapter focuses on the commercially deployed virtual prototyping use cases for architecture exploration and system-level power analysis.

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Abbreviations

API:

Application Programming Interface

ASIC:

Application-Specific Integrated Circuit

AT:

Approximately Timed

AT-BP:

Approximately Timed Base Protocol

AV:

Architects View

AXI:

Advanced eXtensible Interface

CA:

Cycle Accurate

CPU:

Central Processing Unit

DDR:

Double Data Rate

DMA:

Direct Memory Access

DMI:

Direct Memory Interface

DRAM:

Dynamic Random-Access Memory

DSP:

Digital Signal Processor

DVFS:

Dynamic Voltage and Frequency Scaling

ECU:

Electronic Control Unit

FPGA:

Field-Programmable Gate Array

FT:

Fast Timed

GFRBM:

Generic File Reader Bus Master

GPU:

Graphics Processing Unit

HAPS:

High-performance ASIC Prototyping System

HDL:

Hardware Description Language

HSCD:

Hardware/Software Codesign

HW:

Hardware

IP:

Intellectual Property

ISS:

Instruction-Set Simulator

LT:

Loosely Timed

MCO:

Multi-Core Optimization

MPSoC:

Multi-Processor System-on-Chip

OS:

Operating System

PMU:

Power Management Unit

QoS:

Quality of Service

RFTS:

Run Fast Then Stop

RTL:

Register Transfer Level

SCML:

SystemC Modeling Library

SLP:

System-Level Power

SMP:

Symmetric Multi-Processing

SoC:

System-on-Chip

SW:

Software

TCL:

Tool Command Language

TLM:

Transaction-Level Model

UPF:

Unified Power Format

VPU:

Virtual Processing Unit

VP:

Virtual Prototype

References

  1. AMBA AXI and ACE Protocol Specification (2013). http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/index.html

  2. AMBA-PV Extensions to TLM Developer Guide (2015). http://infocenter.arm.com/help/topic/com.arm.doc.dui0846f/DUI0846F_ambapv_extensions_to_tlm_2-0_dg.pdf

  3. ARM Fast Models. http://www.arm.com/products/tools/models/fast-models

  4. Bailey B et al (eds) (2010) TLM-driven design and verification methodology. Cadence Design Systems, San Jose. https://www.synopsys.com/vpbook

    Google Scholar 

  5. Balarin F et al (1997) Hardware-software co-design of embedded systems: the POLIS approach. Kluwer Academic Publishers, Boston

    Book  MATH  Google Scholar 

  6. Barroso L, Holzle U (2007) The case for energy-proportional computing. Computer 40(12):33–37. doi: 10.1109/MC.2007.443

    Article  Google Scholar 

  7. Datta S, Bonnet C, Nikaein N (2012) Android power management: current and future trends. In: 2012 first IEEE workshop on enabling technologies for smartphone and internet of things (ETSIoT), pp 48–53. doi: 10.1109/ETSIoT.2012.6311253

  8. Fadi Aboud IC (2014) Balancing power performance and user experience using virtual prototyping. In: Proceedings of the synopsys users group conference (SNUG), Israel. https://www.synopsys.com/news/pubs/snug/2014/israel/B2_Aboud_pres_user.pdf

  9. Fischer B, Cech C, Muhr H (2014) Power modeling and analysis in early design phases. In: Proceedings of design, automation and test in Europe conference and exhibition (DATE), pp 1–6. doi: 10.7873/DATE.2014.210

  10. Flynn D, Aitken R, Gibbons A, Shi K (2007) Low power methodology manual for system-on-chip design. Springer, New York

    Google Scholar 

  11. IEEE Standard for Design and Verification of Low-Power Integrated Circuits (2015). http://standards.ieee.org/getieee/1801/download/1801-2015.pdf

    Google Scholar 

  12. IEEE Standard for Standard SystemC Language Reference Manual (2011). http://standards.ieee.org/getieee/1666/download/1666-2011.pdf

    Google Scholar 

  13. Kempf T, Doerper M, Leupers R, Ascheid G, Meyr H, Kogel T, Vanthournout B (2005) A modular simulation framework for spatial and temporal task mapping onto multi-processor SoC platforms. In: Proceedings of design, automation and test in Europe, vol 2, pp 876–881. doi: 10.1109/DATE.2005.21

  14. Kogel T (2006) Peripheral modeling for platform driven ESL design. In: Burton M, Morawiec A (eds) Platform based design at the electronic system level. Springer, Dordrecht, pp 71–85

    Chapter  Google Scholar 

  15. Kogel T (2013) Designing the right architecture, SoC interconnect and memory optimization with synopsys platform architect. Synopsys whitepaper. https://www.synopsys.com/cgi-bin/proto/pdfdla/pdfr1.cgi?file=pa_soc_v4_wp.pdf

  16. Kogel T (2016) Optimizing DDR memory subsystem efficiency, Part 1: the unpredictable memory bottleneck. Synopsys whitepaper. https://www.synopsys.com/cgi-bin/proto/pdfdla/pdfr1.cgi?file=optimizing-ddr-efficiency-p1-wp.pdf

  17. Kogel T (2016) Optimizing DDR memory subsystem efficiency, Part 2: case study. Synopsys whitepaper. https://www.synopsys.com/cgi-bin/proto/pdfdla/pdfr1.cgi?file=optimizing-ddr-efficiency-p2-wp.pdf

  18. Kogel T et al (2005) Integrated system-level modeling of network-on-chip enabled multi-processor platforms. Springer, Dordrecht

    MATH  Google Scholar 

  19. Lecler J-J, Baillieu G (2011) Application driven network-on-chip architecture exploration & refinement for a complex SoC. Des Autom Embed Syst 15(2):133–158. doi: 10.1007/s10617-011-9075-5

    Article  Google Scholar 

  20. Patel S, Sood B, Semiconductor F (2014) Quick, re-usable and cost effective approach to create accurate models using synopsys platform architect framework for early system level performance analysis. In: Proceedings of the synopsys users group conference (SNUG), India. http://www.synopsys.com/news/pubs/snug/2014/India/paper_sood.pdf

  21. Reyes V (2012) Virtualized fault injection methods in the context of the ISO 26262 standard. SAE Int J Passenger Cars Electron Electr Syst 5(1):9–16

    Article  MathSciNet  Google Scholar 

  22. Schurmans S, Zhang D, Auras D, Leupers R, Ascheid G, Chen X, Wang L (2013) Creation of ESL power models for communication architectures using automatic calibration. In: 2013 50th ACM/EDAC/IEEE design automation conference (DAC), pp 1–6. doi: 10.1145/2463209.2488804

  23. Schutter TD (ed) (2014) Better software. Faster! best practices in virtual prototyping. Synopsys Press. https://www.synopsys.com/vpbook

  24. Skrzeszewski TK, Intel Corp. (2015) ATOM mobile SoC performance and power architecture exploration. In: Synopsys users group conference (SNUG), Santa Clara. http://www.synopsys.com/news/pubs/snug/2015/silicon-valley/mb08_skrzeszewski_paper.pdf

  25. Synopsys DW TLM library. http://www.synopsys.com/Prototyping/VirtualPrototyping/VPModels/Pages/DW-TLM-Library.aspx

  26. Teich J (2012) Hardware/software codesign: the past, the present, and predicting the future. Proc IEEE 100(Special Centennial Issue):1411–1430. doi: 10.1109/JPROC.2011.2182009

  27. The SystemC Modeling Library (SCML). http://www.synopsys.com/cgi-bin/slcw/kits/reg.cgi

  28. Tool Command Language (TCL). http://www.tcl.tk

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Acknowledgements

The author acknowledges Tom De Schutter for contributing the sections on software development and on system validation to the introduction of this chapter as well as Alan Gibbons for contributing the section on system level power analysis to the introduction of this chapter.

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Authors and Affiliations

  1. Synopsys, Inc., Aachen, Germany

    Tim Kogel

Authors
  1. Tim Kogel
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Correspondence to Tim Kogel .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Kogel, T. (2017). Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_34

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