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Hardware/Software Codesign Across Many Cadence Technologies

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Book cover Handbook of Hardware/Software Codesign

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Abstract

Cadence offers many technologies and methodologies for hardware/software codesign of advanced electronic and software systems. This chapter outlines many of these technologies and provides a brief overview of their key use models and methodologies. These include advanced verification, prototyping – both virtual and real, emulation, high-level synthesis, design of an Application-Specific Instruction-set Processor (ASIP), and software-driven verification approaches.

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Abbreviations

ADAS:

Advanced Driver Assistance System

API:

Application Programming Interface

ASIC:

Application-Specific Integrated Circuit

ASIP:

Application-Specific Instruction-set Processor

AXI:

Advanced eXtensible Interface

CNN:

Convolutional Neural Network

CPF:

Common Power Format

DMA:

Direct Memory Access

DSP:

Digital Signal Processor

DUT:

Design Under Test

ECO:

Engineering Change Order

EDA:

Electronic Design Automation

ESL:

Electronic System Level

FFT:

Fast Fourier Transform

FIFO:

First-In First-Out

FPGA:

Field-Programmable Gate Array

HLS:

High-Level Synthesis

HSCD:

Hardware/Software Codesign

HVL:

Hardware Verification Language

HW:

Hardware

IDE:

Integrated Development Environment

IP:

Intellectual Property

ISA:

Instruction-Set Architecture

ISS:

Instruction-Set Simulator

JTAG:

Joint Test Action Group

LISA:

Language for Instruction-Set Architectures

MAC:

Multiply-Accumulator

NoC:

Network-on-Chip

OFDM:

Orthogonal Frequency Dependent Multiplexing

OS:

Operating System

OVM:

Open Verification Methodology

PCI:

Peripheral Component Interconnect

PC:

Personal Computer

RISC:

Reduced Instruction-Set Processor

RTL:

Register Transfer Level

SDK:

Software Development Kit

SDS:

System Development Suite

SIMD:

Single Instruction, Multiple Data

SW:

Software

TIE:

Tensilica Instruction Extension

TLM:

Transaction-Level Model

UML:

Unified Modeling Language

UPF:

Unified Power Format

USB:

Universal Serial Bus

UVM:

Universal Verification Methodology

VLIW:

Very Long Instruction Word

VMM:

Verification Methodology Manual

VP:

Virtual Prototype

VSIA:

Virtual Socket Interface Alliance

VSP:

Virtual System Platform

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Authors and Affiliations

  1. Cadence Design Systems, San Jose, CA, USA

    Grant Martin, Frank Schirrmeister & Yosinori Watanabe

Authors
  1. Grant Martin
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  2. Frank Schirrmeister
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  3. Yosinori Watanabe
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Corresponding author

Correspondence to Grant Martin .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Martin, G., Schirrmeister, F., Watanabe, Y. (2017). Hardware/Software Codesign Across Many Cadence Technologies. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_33

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