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Memory-Aware Optimization of Embedded Software for Multiple Objectives

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Handbook of Hardware/Software Codesign

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Abstract

Information processing in Cyber-Physical Systems (CPSs) has to respect a variety of constraints and objectives such as response and execution time, energy consumption , Quality of Service (QoS), size, and cost. Due to the large impact of the size of memories on their energy consumption and access times, an exploitation of memory characteristics offers a large potential for optimizations. In this chapter, we will describe optimization approaches proposed by our research groups. We will start with optimizations for single objectives, such as energy consumption and execution time. As a consequence of considering hard real-time systems , special attention is on the minimization of the Worst-Case Execution Time (WCET) within compilers . Three WCET reduction techniques are analyzed: exploitation of scratchpads, instruction cache locking, and cache partitioning for multitask systems. The last section presents an approach for considering trade-offs between multiple objectives in the design of a cyber-physical sensor system for the detection of bio-viruses.

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Abbreviations

CFG:

Control-Flow Graph

CPS:

Cyber-Physical System

CPU:

Central Processing Unit

CRPD:

Cache-Related Preemption Delay

DRAM:

Dynamic Random-Access Memory

FIFO:

First-In First-Out

GA:

Genetic Algorithm

GPU:

Graphics Processing Unit

ILP:

Integer Linear Program

LRU:

Least-Recently Used

MMU:

Memory Management Unit

PAMONO:

Plasmon-Assisted Microscopy of Nano-Objects

QoS:

Quality of Service

SPM:

Scratchpad Memory

SRAM:

Static Random-Access Memory

SVM:

Support Vector Machine

WCC:

WCET-aware C Compiler

WCEC:

Worst-Case Energy Consumption

WCEP:

Worst-Case Execution Path

WCET:

Worst-Case Execution Time

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Acknowledgements

Part of the work on this section has been supported by Deutsche Forschungsgemeinschaft (DFG) within the Collaborative Research Center SFB 876 “Providing Information by Resource-Constrained Analysis,” project B2. URL: http://sfb876.tu-dortmund.de

Author information

Authors and Affiliations

  1. Computer Science, TU Dortmund University, D-44221, Dortmund, Germany

    Peter Marwedel & Olaf Neugebauer

  2. Institute of Embedded Systems, Hamburg University of Technology, D-21071, Hamburg, Germany

    Heiko Falk

Authors
  1. Peter Marwedel
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  2. Heiko Falk
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  3. Olaf Neugebauer
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Correspondence to Peter Marwedel .

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Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Marwedel, P., Falk, H., Neugebauer, O. (2017). Memory-Aware Optimization of Embedded Software for Multiple Objectives. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_27

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