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Parallel Simulation

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Handbook of Hardware/Software Codesign

Abstract

The SystemC standard is widely used in industry and academia to model and simulate electronic system-level designs. However, despite the availability of multi-core processor hosts, the reference SystemC simulator is still based on sequential Discrete Event Simulation (DES) which executes only a single thread at any time.

In recent years, parallel SystemC simulators have been proposed which run multiple threads in parallel based on Parallel Discrete Event Simulation (PDES) semantics. While this can improve the simulator run time by an order of magnitude, synchronous PDES requires careful dependency analysis of the model and still limits the parallel execution to threads that run at the same simulation time.

In this chapter, we review the classic DES and PDES algorithms and then present a state-of-the-art approach called Out-of-Order Parallel Discrete Event Simulation (OOO PDES) which breaks the traditional time cycle barrier and executes threads in parallel and out of order (ahead of time) while maintaining the standard SystemC modeling semantics. Specifically, we present our Recoding Infrastructure for SystemC (RISC) that consists of a dedicated SystemC compiler and advanced parallel simulator. RISC provides an open-source reference implementation of OOO PDES and achieves fastest simulation speed for traditional SystemC models without any loss of accuracy.

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Abbreviations

AST:

Abstract Syntax Tree

DE:

Discrete Event

DES:

Discrete Event Simulation

DUT:

Design Under Test

ESL:

Electronic System Level

OOO PDES:

Out-of-Order Parallel Discrete Event Simulation

PDES:

Parallel Discrete Event Simulation

RISC:

Recoding Infrastructure for SystemC

SG:

Segment Graph

SLDL:

System-Level Description Language

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Acknowledgements

This work has been supported in part by substantial funding from Intel Corporation. The authors thank Intel Corporation for the valuable support and fruitful collaboration. The authors also thank the anonymous reviewers for valuable suggestions to improve this chapter.

Author information

Authors and Affiliations

  1. Center for Embedded and Cyber-physical Systems, Department of Electrical Engineering and Computer Science, The Henry Samueli School of Engineering, University of California, Irvine, 92697-2620, Irvine, CA, USA

    Rainer Dömer

  2. Center for Embedded and Cyber-physical Systems, University of California, Irvine, 92697-2620, Irvine, CA, USA

    Guantao Liu & Tim Schmidt

Authors
  1. Rainer Dömer
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  2. Guantao Liu
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  3. Tim Schmidt
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Corresponding author

Correspondence to Rainer Dömer .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Dömer, R., Liu, G., Schmidt, T. (2017). Parallel Simulation. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_19

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