Encyclopedia of Database Systems

2018 Edition
| Editors: Ling Liu, M. Tamer Özsu

Processor Cache

  • Peter BonczEmail author
Reference work entry
DOI: https://doi.org/10.1007/978-1-4614-8265-9_684


CPU cache; Data cache; Instruction cache; L1 cache; L2 cache; L3 cache; Translation Lookaside Buffer (TLB)


To hide the high latencies of DRAM access, modern computer architecture now features a memory hierarchy that besides DRAM also includes SRAM cache memories, typically located on the CPU chip. Memory access first check these caches, which takes only a few cycles. Only if the needed data is not found, an expensive memory access is needed.

Key Points

CPU caches are SRAM memories located on the CPU chip, intended to hide the high latency of accessing off-chip DRAM memory. Caches are organized in cache lines (typically 64 bytes). In a fully-associative cache, each memory line can be stored in any location of the cache. To make checking the cache fast, however, CPU caches tend to have limited associativity, such that storage of a particular cache line is possible in only two or FOUR locations. Thus only two or four locations need to be checked during lookup (these...

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.CWIAmsterdamThe Netherlands

Section editors and affiliations

  • Anastasia Ailamaki
    • 1
  1. 1.Informatique et CommunicationsEcole Polytechnique Fédérale de LausanneLausanneSwitzerland