Encyclopedia of Big Data Technologies

2019 Edition
| Editors: Sherif Sakr, Albert Y. Zomaya

Hardware-Assisted Compression

  • K. SayoodEmail author
  • S. Balkir
Reference work entry
DOI: https://doi.org/10.1007/978-3-319-77525-8_311


Video compression: Compact representation of digital video.

Discrete cosine transform (DCT): An orthonormal transform used in many compression applications.

Arithmetic coding: An entropy coding technique that is particularly useful for alphabets with a skewed probability distribution.

LZ77: A dictionary based sequence compression algorithm which adaptively builds its dictionary through an optimal parsing of the “past” of the sequence.


The information revolution has resulted in the ubiquity of the use of compression. As the explosion in the spread of information persists, the need for energy efficient compression is driving the development of more and more hardware-assisted compression, despite the increasing power of processors. The need is most where the resource constraints are most severe – where the constraints are relative to the application. Video compression deals with a huge amount of temporally sensitive information and thus is highly time-constrained....

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  1. Alvarado AS, Lakshminarayan C, Principe JC (2012) Time-based compression and classification of heartbeats. IEEE Trans Biomed Eng 59(6):1641–1648CrossRefGoogle Scholar
  2. Amarú L, Gaillardon P-E, Burg A, De Micheli G (2014) Data compression via logic synthesis. In: 19th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, pp 628–633Google Scholar
  3. Amer I, Badawy W, Jullien G (2005) A high-performance hardware implementation of the H.264 simplified 8/spl times/8 transformation and quantization [video coding]. In: IEEE International Conference on acoustics, speech, and signal processing, proceedings (ICASSP’05)., vol 2. IEEE, pp ii–1137Google Scholar
  4. Anastasi G, Conti M, Francesco MD, Passarella A (2009) Energy conservation in wireless sensor networks: a survey. Ad Hoc Netw 7(3):537–568CrossRefGoogle Scholar
  5. Benini L, Bruni D, Macii A, Macii E (2002) Hardware-assisted data compression for energy minimization in systems with embedded processors. In: Proceedings of the conference on design, automation and test in Europe. IEEE Computer Society, pp 449Google Scholar
  6. Cardoso BB, Gomes JGRC (2014) CMOS imager with focal-plane image compression based on the EZW algorithm. In: 2014 IEEE 5th Latin American symposium on circuits and systems. pp 1–4Google Scholar
  7. Chang T-S, Kung C-S, Jen C-W (2000) A simple processor core design for DCT/IDCT. IEEE Trans Circuits Syst Video Technol 10(3):439–447CrossRefGoogle Scholar
  8. Cheng J-M, Duyanovich LM (1995) Fast and highly reliable IBMLZ1 compression chip and algorithm for storage. In: IEEE [IEE95]. pp 143–154Google Scholar
  9. Chen YH, Sze V (2015) A deeply pipelined cabac decoder for HEVC supporting level 6.2 high-tier applications. IEEE Trans Circuits Syst Video Technol 25(5):856–868CrossRefGoogle Scholar
  10. Chen S, Bermak A, Wang Y (2011) A CMOS image sensor with on-chip image compression based on predictive boundary adaptation and memoryless QTD algorithm. IEEE Trans Very Large Scale Integr (VLSI) Syst 19(4):538–547CrossRefGoogle Scholar
  11. Cho S, Kim H, Kim HY, Kim M (2015) Efficient in-loop filtering across tile boundaries for multi-core HEVC hardware decoders with 4K/8K-UHD video applications. IEEE Trans Multimedia 17(6):778–791CrossRefGoogle Scholar
  12. Deepu CJ, Lian Y (2015) A joint QRS detection and data compression scheme for wearable sensors. IEEE Trans Biomed Eng 62(1):165–175CrossRefGoogle Scholar
  13. Deepu CJ, Zhang XY, Wong DLT, Lian Y (2016) An ECG-on-chip with joint QRS detection & data compression for wearable sensors. In: 2016 IEEE international symposium on circuits and systems (ISCAS). IEEE, pp 2908–2908Google Scholar
  14. Ekman M, Stenstrom P (2005) A robust main-memory compression scheme. In: ACM SIGARCH computer architecture news, vol 33. IEEE Computer Society, pp 74–85Google Scholar
  15. Estevo Filho R de M, Gomes JGRC, Petraglia A (2013) Codebook improvements for a CMOS imager with focal-plane vector quantization. In: 2013 IEEE 4th Latin American symposium on circuits and systems (LASCAS), pp 1–4Google Scholar
  16. Franaszek PA, Heidelberger P, Poff DE, Robinson JT (2001) Algorithms and data structures for compressed-memory machines. IBM J Res Dev 45(2):245–258CrossRefGoogle Scholar
  17. Gong D, He Y, Cao Z (2004) New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse. IEEE Trans Circuits Syst Video Technol 14(4):405–415CrossRefGoogle Scholar
  18. Hasan KK, Ngah UK, Salleh MFM (2014) Efficient hardware-based image compression schemes for wireless sensor networks: a survey. Wirel Pers Commun 77(2):1415–1436CrossRefGoogle Scholar
  19. ITU-T Recomendation H.261 (1993) Video codec for audiovisual services at p × 64 kbit/sGoogle Scholar
  20. Karargyris A, Bourbakis N (2010) Wireless capsule endoscopy and endoscopic imaging: a survey on various methodologies presented. IEEE Eng Med Biol Mag 29(1):72–83CrossRefGoogle Scholar
  21. Khurana G, Kassim AA, Chua TP, Mi MB (2006) A pipelined hardware implementation of in-loop deblocking filter in H.264/AVC. IEEE Trans Consum Electron 52(2):536–540CrossRefGoogle Scholar
  22. Kim S, Lee D, Kim H, Truong NX, Kim J-S (2015) An enhanced one-dimensional SPIHT algorithm and its implementation for TV systems. Displays 40: 68–77CrossRefGoogle Scholar
  23. Kjelso M, Gooch M, Jones S (1996) Design and performance of a main memory hardware data compressor. In: Beyond 2000: Proceedings of the 22nd EUROMICRO conference hardware and software design strategies, EUROMICRO 96. IEEE, pp 423–430Google Scholar
  24. Leon-Salas WD, Balkir S, Sayood K, Hoffman MW, Schemm N (2006) A CMOS imager with focal plane compression. In: Proceedings of IEEE international symposium on circuits and systems, ISCAS 2006. IEEE, pp 4–ppGoogle Scholar
  25. Leon-Salas WD, Balkir S, Sayood K, Schemm N, Hoffman MW (2007) A CMOS imager with focal plane compression using predictive coding. IEEE J Solid-State Circuits 42(11):2555–2572CrossRefGoogle Scholar
  26. Lin Z, Hoffman MW, Leon WD, Schemm N, Balkir S (2008) A CMOS image sensor with focal plane spiht image compression. In: 2008 IEEE international symposium on circuits and systems. pp 2134–2137Google Scholar
  27. Loeffler C, Ligtenberg A, Moschytz GS (1989) Practical fast 1-D DCT algorithms with 11 multiplications. In: 1989 international conference on acoustics, speech, and signal processing, ICASSP-89. IEEE, pp 988–991Google Scholar
  28. Martisius I, Birvinskas D, Jusas V, Tamosevicius Z (2011) A 2-D DCT hardware codec based on loeffler algorithm. Elektronika ir Elektrotechnika 113(7):47–50Google Scholar
  29. Mitchell JL, Pennebaker WB, Fogg CE, and LeGall DJ (1997) MPEG video compression standard. Chapman and Hall, LondonCrossRefGoogle Scholar
  30. Meher PK, Park SY, Mohanty BK, Lim KS, Yeo C (2014) Efficient integer DCT architectures for HEVC. IEEE Trans Circuits Syst Video Technol 24(1):168–178CrossRefGoogle Scholar
  31. Nunez-Yanez YL, Chouliaras VA, Alfonso D, Rovati FS (2006) Hardware assisted rate distortion optimization with embedded cabac accelerator for the H.264 advanced video codec. IEEE Trans Consum Electron 52(2):590–597CrossRefGoogle Scholar
  32. Oliveira FDVR, Haas HL, Gomes JGRC, Petraglia A (2013) CMOS imager with focal-plane analog image compression combining DPCM and VQ. IEEE Trans Circuits Syst I: Regular Papers 60(5):1331–1344CrossRefGoogle Scholar
  33. Olyaei A, Genov R (2007) Focal-plane spatially oversampling cmos image compression sensor. IEEE Trans Circuits Syst I Regul Pap 54(1):26–34CrossRefGoogle Scholar
  34. Park J-S, Nam W-J, Han S-M, Lee S-S (2012) 2-D large inverse transform (16 × 16, 32 × 32) for HEVC (high efficiency video coding). JSTS: J Semicond Technol Sci 12(2):203–211CrossRefGoogle Scholar
  35. Pastuszak G (2014) Hardware architectures for the H.265/HEVC discrete cosine transform. IET Image Process 9(6):468–477CrossRefGoogle Scholar
  36. Pirsch P, Demassieux N, Gehrke W (1995) VLSI architectures for video compression-a survey. Proc IEEE 83(2):220–246CrossRefGoogle Scholar
  37. Peng B, Ding D, Zhu X, Yu L (2013) A hardware cabac encoder for HEVC. In: 2013 IEEE international symposium on circuits and systems (ISCAS2013), pp 1372–1375Google Scholar
  38. Rao KR, Yip P (1990) Discrete Cosine transform – algorithms, advantages, applications. Academic Press, San DiegozbMATHGoogle Scholar
  39. Ranjan A, Raha A, Raghunathan V, Raghunathan A (2017) Approximate memory compression for energy-efficiency. In: 2017 IEEE/ACM international symposium on low power electronics and design (ISLPED), pp 1–6Google Scholar
  40. Said A, Pearlman WA (1996) A new fast and efficient coder based on set partitioning in hierarchical trees. IEEE Trans Circuits Syst Video Technol 6:243–250CrossRefGoogle Scholar
  41. Sarmiento D, Pang Z, Sanchez MF, Chen Q, Tenhunen H, Zheng L-R (2010) Mobile wireless sensor system for tracking and environmental supervision. In: 2010 IEEE international symposium on industrial electronics (ISIE). IEEE, pp 470–477Google Scholar
  42. Sardashti S, Wood DA (2014) Decoupled compressed cache: exploiting spatial locality for energy optimization. IEEE Micro 34(3):91–99CrossRefGoogle Scholar
  43. Sardashti S, Arelakis A, Stenström P, Wood DA (2015) A primer on compression in the memory hierarchy. Synthesis Lect Comput Archit 10(5):1–86CrossRefGoogle Scholar
  44. Sayood K (2017) Introduction to data compression, 5th edn. Morgan Kauffman-Elsevier, San FranciscozbMATHGoogle Scholar
  45. Schmitz JA, Gharzai MK, Balkır S, Hoffman MW, White DJ, Schemm N (2017) A 1000 frames/s vision chip using scalable pixel-neighborhood-level parallel processing. IEEE J Solid-State Circuits 52(2):556–568CrossRefGoogle Scholar
  46. Turcza P, Duplaga M (2013) Hardware-efficient low-power image processing system for wireless capsule endoscopy. IEEE J Biomed Health Inf 17(6): 1046–1056CrossRefGoogle Scholar
  47. Tremaine RB, Franaszek PA, Robinson JT, Schulz CO, Smith TB, Wazlowski ME, Bland PM (2001) IBM memory expansion technology (MXT). IBM J Res Dev 45(2):271–285CrossRefGoogle Scholar
  48. Wahid K, Ko S-B, Teng D (2008) Efficient hardware implementation of an image compressor for wireless capsule endoscopy applications. In: IEEE international joint conference on neural networks, IJCNN 2008. IEEE World congress on computational intelligence. IEEE, pp 2761–2765Google Scholar
  49. Wang HT, WD-Salas L (2012) A multiresolution algorithm for focal-plane compression. In: 2012 IEEE international symposium on circuits and systems. pp 926–929Google Scholar
  50. Ziv J, Lempel A (1977) A universal algorithm for data compression. IEEE Trans Inf Theory IT-23(3): 337–343MathSciNetzbMATHCrossRefGoogle Scholar
  51. Zhao J, Li S, Chang J, Byrne JL, Ramirez LL, Lim K, Xie Y, Faraboschi P (2015) Buri: scaling big-memory computing with hardware-based memory expansion. ACM Trans Archit Code Optim (TACO) 12(3):31Google Scholar

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Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of Nebraska-LincolnLincolnUSA