Skip to main content

Memory Hierarchy

  • Reference work entry
  • First Online:
Encyclopedia of Database Systems
  • 116 Accesses

Synonyms

Hierarchical memory system

Definition

A Hierarchical Memory System – or Memory Hierarchy for short – is an economical solution to provide computer programs with (virtually) unlimited fast memory, taking advantage of locality and cost-performance of memory technology. Computer storage and memory hardware – from disk drives to DRAM main memory to SRAM CPU caches – shares the limitation that as they became faster, they become more expensive (per capacity), and thus smaller. Consequently, memory hierarchies are organized into several levels, starting from huge and inexpensive but slow disk systems to DRAM main memory and SRAM CPU caches (both off and on chip) to registers in the CPU core. Each level closer to the CPU is faster but smaller than the next level one step down in the hierarchy. Memory hierarchies exploit the principle of locality, i.e., the property that computer programs do not access all their code and data uniformly, but rather focus on referencing only small...

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 4,499.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 6,499.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Recommended Reading

  1. Ailamaki A, Boncz PA, Manegold S, editors. In: Proceedings of the 1st Workshop on Data Management on New Hardware; 2005.

    Google Scholar 

  2. Ailamaki A, Boncz PA, Manegold S, editors. In: Proceedings of the 2nd Workshop on Data Management on New Hardware; 2006.

    Google Scholar 

  3. Ailamaki A, Luo Q, editors. In: Proceedings of the 3rd Workshop on Data Management on New Hardware; 2007.

    Google Scholar 

  4. Ailamaki AG, DeWitt DJ., Hill MD, Wood DA. DBMSs on a modern processor: where does time go? In: Proceedings of the 25th International Conference on Very Large Data Bases; 1999. p. 266–77.

    Google Scholar 

  5. Boncz PA, Manegold S, Kersten M. Database architecture optimized for the New Bottleneck: memory access. In: Proceedings of the 25th International Conference on Very Large Data Bases; 1999. p. 54–65.

    Google Scholar 

  6. Denning PJ. The working set model for program behaviour. Commun ACM. 1968;11(5):323–33.

    Article  MathSciNet  MATH  Google Scholar 

  7. Denning PJ. The locality principle. Commun ACM. 2005;48(7):19–24.

    Article  Google Scholar 

  8. Hennessy JL, Patterson DA. Computer architecture – a quantitative approach. 3rd ed. San Mateo: Morgan Kaufmann; 2003.

    MATH  Google Scholar 

  9. Hill MD, Smith AJ. Evaluating associativity in CPU caches. IEEE Trans Comput. 1989;38(12):1612–30.

    Article  Google Scholar 

  10. Kilburn T, Edwards DBC, Lanigan MI, Sumner FH. One-level storage system. IRE Trans Electronic Comput. 1962;2(11):223–35.

    Article  Google Scholar 

  11. Manegold S. Understanding, modeling, and improving main-memory database performance. PhD thesis, Universiteit van Amsterdam, Amsterdam, The Netherlands; 2002.

    Google Scholar 

  12. Moore GE. Cramming more components onto integrated circuits. Electronics. 1965;38(8):114–7.

    Google Scholar 

  13. Ross K, Luo Q, editors. In: Proceedings of the 3rd Workshop on Data Management on New Hardware; 2007.

    Google Scholar 

  14. Shatdal A, Kant C, Naughton J. Cache conscious algorithms for relational query processing. In: Proceedings of the 20th International Conference on Very Large Data Bases; 1994. p. 510–2.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Stefan Manegold .

Editor information

Editors and Affiliations

Section Editor information

Rights and permissions

Reprints and permissions

Copyright information

© 2018 Springer Science+Business Media, LLC, part of Springer Nature

About this entry

Check for updates. Verify currency and authenticity via CrossMark

Cite this entry

Manegold, S. (2018). Memory Hierarchy. In: Liu, L., Özsu, M.T. (eds) Encyclopedia of Database Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-8265-9_657

Download citation

Publish with us

Policies and ethics