Clock Skew Optimization for Peak Current Reduction L. BeniniP. VuillodG. De Micheli OriginalPaper 01 June 1997 Pages: 117 - 130
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews Hong-Yean HsiehWentai LiuRalph Cavin III OriginalPaper 01 June 1997 Pages: 131 - 147
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations Josè Luis NevesEby G. Friedman OriginalPaper 01 June 1997 Pages: 149 - 161
Useful-Skew Clock Routing with Gate Sizing for Low Power Design Joe Gufeng XiWayne Wei-Ming Dai OriginalPaper 01 June 1997 Pages: 163 - 179
Clock Distribution Methodology for PowerPC™ Microprocessors Shantanu GangulyDaksh LehtherSatyamurthy Pullela OriginalPaper 01 June 1997 Pages: 181 - 189
Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology D.J. HathawayR.R. HabraS.J. Rothman OriginalPaper 01 June 1997 Pages: 191 - 198
Practical Bounded-Skew Clock Routing Andrew B. KahngC.-W. Albert Tsao OriginalPaper 01 June 1997 Pages: 199 - 215
A Clock Methodology for High-Performance Microprocessors Keith M. CarrigAlbert M. ChuRichard J. Weiss OriginalPaper 01 June 1997 Pages: 217 - 224
Optical Clock Distribution in Electronic Systems Stuart K. TewksburyLawrence A. Hornak OriginalPaper 01 June 1997 Pages: 225 - 246
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits Kris GajEby G. FriedmanMarc J. Feldman OriginalPaper 01 June 1997 Pages: 247 - 276