1. Multilevel Bipolar Memristor Model Considering Deviations of Switching Parameters in the Verilog-A Language

   • G. S. Teplov
   • E. S. Gornev

   OriginalPaper 13 June 2019 Pages: 131 - 142

   

2. Logical C-Element on STG DICE Trigger for Asynchronous Digital Devices Resistant to Single Nuclear Particles

   • Yu. V. Katunin
   • V. Ya. Stenin

   OriginalPaper 13 June 2019 Pages: 143 - 156

   

3. Monte Carlo Simulation of Defects of a Trench Profile in the Process of Deep Reactive Ion Etching of Silicon

   • M. K. Rudenko
   • A. V. Myakon’kikh
   • V. F. Lukichev

   OriginalPaper 13 June 2019 Pages: 157 - 166

   

4. Methods and Algorithms for the Logical-Topological Design of Microelectronic Circuits at the Valve and Inter-Valve Levels for Promising Technologies with a Vertical Transistor Gate

   • G. A. Ivanova
   • D. I. Ryzhova
   • A. L. Stempkovskii

   OriginalPaper 13 June 2019 Pages: 167 - 175

   

5. Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip

   • S. V. Gavrilov
   • D. A. Zheleznikov
   • V. I. Enns

   OriginalPaper 13 June 2019 Pages: 176 - 186

   

6. Extracting a Logic Gate Network from a Transistor-Level CMOS Circuit

   • D. I. Cheremisinov
   • L. D. Cheremisinova

   OriginalPaper 13 June 2019 Pages: 187 - 196

   

7. Reflection Spectra Modification of Diazoquinone-Novolak Photoresist Implanted with B and P Ions

   • D. I. Brinkevich
   • A. A. Kharchenko
   • Yu. N. Yankovskii

   OriginalPaper 13 June 2019 Pages: 197 - 201