1. Editorial—Special issue on partial scan design

   • Vishwani D. Agrawal

   EditorialNotes Pages: 5 - 6

2. Partial scan and symbolic test at the register-transfer level

   • Johannes Steensma
   • Francky Catthoor
   • Hugo De Man

   High-Level Design Pages: 7 - 23

3. Partial scan design of register-transfer level circuits

   • Rajesh Gupta
   • Melvin A. Breuer

   High-Level Design Pages: 25 - 46

4. Partial scan flip-flop selection by use of empirical testability

   • Kee S. Kim
   • Charles R. Kime

   Testability Analysis Based Algorithms Pages: 47 - 59

5. Testability-based partial scan analysis

   • Prashant S. Parikh
   • Miron Abramovici

   Testability Analysis Based Algorithms Pages: 61 - 70

6. An optimal algorithm for cycle breaking in directed graphs

   • Tatiana Orenstein
   • Zvi Kohavi
   • Irith Pomeranz

   Structure-Based Algorithms Pages: 71 - 81

7. An exact algorithm for selecting partial scan flip-flops

   • Srimat T. Chakradhar
   • Arun Balakrishnan
   • Vishwani D. Agrawal

   Structure-Based Algorithms Pages: 83 - 93

8. A three-stage partial scan design method to ease ATPG

   • Shang-E Tai
   • Debashis Bhattacharya

   Structure-Based Algorithms Pages: 95 - 104

9. Design of testable sequential circuits by repositioning flip-flops

   • Sujit Dey
   • Srimat T. Chakradhar

   Structure-Based Algorithms Pages: 105 - 114

10. Partial scan design and test sequence generation based on reduced scan shift method

    • Yoshinobu Higami
    • Seiji Kajihara
    • Kozo Kinoshita

    Test Length Minimization Pages: 115 - 124

11. Integration of partial scan and built-in self-test

    • Chih-Jen Lin
    • Yervant Zorian
    • Sudipta Bhawmik

    Self-Test with Partial Scan Pages: 125 - 137