1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 123 - 123

2. Logical redundancies in irredundant combinational circuits

   • Susanta Chakraborty
   • Debesh K. Das
   • Bhargab B. Bhattacharya

   OriginalPaper Pages: 125 - 130

3. Delay fault simulation of sequential circuits

   • Kanji Hirabayashi

   OriginalPaper Pages: 131 - 135

4. An architectural level test generator based on nonlinear equation solving

   • Jaushin Lee
   • Janak H. Patel

   OriginalPaper Pages: 137 - 150

5. Aliasing properties of circular MISRs

   • Geetani Edirisooriya
   • John P. Robinson

   OriginalPaper Pages: 151 - 158

6. Test program synthesis for modules and chips having boundary scan

   • Jung-Cheun Lien
   • Melvin A. Breuer

   OriginalPaper Pages: 159 - 180

7. Efficient board interconnect testing using the split boundary scan register

   • Nazar S. Haider
   • Nick Kanopoulos

   OriginalPaper Pages: 181 - 189

8. On the exact ordered binary decision diagram size of totally symmetric functions

   • Mark Heap

   OriginalPaper Pages: 191 - 195