1. Editorial

   • Vishwani D. Agrawal

   Editorial Introduction Pages: 403 - 404

2. Guest Editorial

   • Serge Demidenko

   Editorial Introduction Pages: 407 - 408

3. Test Cycle Count Reduction in a Parallel Scan BIST Environment

   • Bechir Ayari
   • Prab Varma

   OriginalPaper Pages: 409 - 418

4. LFSR-Based Deterministic TPG for Two-Pattern Testing

   • Xiaowei Li
   • Paul Y.S. Cheung
   • Hideo Fujiwara

   OriginalPaper Pages: 419 - 426

5. BIST TPG for Combinational Cluster Interconnect Testing at Board Level

   • Chen-Huan Chiang
   • Sandeep K. Gupta

   OriginalPaper Pages: 427 - 442

6. Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits

   • Yoshinobu Higami
   • Yuzo Takamatsu
   • Kozo Kinoshita

   OriginalPaper Pages: 443 - 451

7. IDDQ Testing of Submicron CMOS—by Cooling?

   • M. Rencz
   • V. Székely
   • B. Courtois

   OriginalPaper Pages: 453 - 461

8. False-Path Removal Using Delay Fault Simulation

   • Marwan A. Gharaybeh
   • Vishwani D. Agrawal
   • Carlos G. Parodi

   OriginalPaper Pages: 463 - 476

9. Reduction of Number of Paths to be Tested in Delay Testing

   • Huawei Li
   • Zhongcheng Li
   • Yinghua Min

   OriginalPaper Pages: 477 - 485

10. Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy

    • Said Hamdioui
    • Ad J. Van De Goor

    OriginalPaper Pages: 487 - 498

11. Dynamic Power Supply Current Testing of CMOS SRAMs

    • Jian Liu
    • Rafic Z. Makki
    • Ayman Kayssi

    OriginalPaper Pages: 499 - 511

12. Testing the Local Interconnect Resources of SRAM-Based FPGA's

    • M. Renovell
    • J.M. Portal
    • Y. Zorian

    OriginalPaper Pages: 513 - 520

13. A Practical Vector Restoration Technique for Large Sequential Circuits

    • Surendra K. Bommu
    • Kiran B. Doreswamy
    • Srimat T. Chakradhar

    OriginalPaper Pages: 521 - 539

14. Static Test Compaction for Scan-Based Designs to Reduce Test Application Time

    • Irith Pomeranz
    • Sudhakar M. Reddy

    OriginalPaper Pages: 541 - 552

15. A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency

    • Satoshi Ohtake
    • Toshimitsu Masuzawa
    • Hideo Fujiwara

    OriginalPaper Pages: 553 - 566